Stéphane Burignat

Garbageless Reversible Implementation of Integer Linear Transformations

Discrete linear transformations are important tools in information processing. Many such transforms are injective and therefore prime candidates for a physically reversible implementation into hardware. We present here reversible digital implementations of different integer transformations on four inputs. The resulting reversible circuit is able to perform both the forward transform and the inverse transform. Which of the two computations that actually is performed, simply depends on the orientation of the circuit when it is inserted in a computer board (if one takes care to provide the encapsulation of symmetrical power supplies). Our analysis indicates that the detailed structure of such a reversible design strongly depends on the prime factors of the determinant of the transform: a determinant equal to a power of 2 leads to an efficient garbage-free design.

Analog/RF performance of sub-100 nm SOI MOSFETs with non-classical gate-source/drain underlap channel design

In this work, we analyze the potential of non-overlap (also known as underlap) source/drain (S/D) channel architecture to improve analog/RF performance metrics of sub-100 nm Ultra Thin Body BOX (UTBB) SOI MOSFETs. It is shown that underlap S/D design results in higher voltage gain (A<inf>VO</inf>) and cut-off frequency (f<inf>T</inf>) along with a broader analog ‘sweet spot’ in nanoscale MOSFETs thus offering new possibilities for analog/RF scaling below 60 nm. The advantages offered by underlap channel design are not limited to lower current levels (∼ 10 µA/µm) but extend up to 100 µA/µm which corresponds to optimum A<inf>VO</inf> and f<inf>T</inf> performance for most circuit applications. For shorter gate length devices, underlap design results in an impressive 20% improvement in f<inf>T</inf> along with a 2 fold enhancement in A<inf>VO</inf>. This work provides new opportunities for realizing future low-power analog/RF design with underlap UTBB MOSFETs.

Underlap channel UTBB MOSFETs for low—power analog/RF applications

In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX (UTBB) fully—depleted (FD) SOI MOSFETs to improve analog/RF performance metrics. It is shown that at lower current levels and shorter gate lengths, underlap UTBB MOSFETs can achieve significant improvement ≫ 1.5 times in key analog/RF metrics over devices designed with conventional S/D architecture. Analog/RF figures of merit are analyzed in terms of spacer—to—straggle ratio (s/σ), a key parameter for the design of underlap devices. Results suggest that underlap S/D design with s/σ ratio of 3.3 is optimum to enhance analog/RF metrics at low current levels (≪ 60 μA/μm). The present work provides new viewpoints for realizing future low—power analog devices/circuits with underlap UTBB FETs.

Drain / substrate coupling impact on DIBL of Ultra Thin Body and BOX SOI MOSFETs with undoped channel

For ultimate MOSFET scaling, Ultra Thin Body and BOX SOI transistors have become of great interest, as they are known to dramatically reduce Short Channel Effects (SCE) while maintaining very high device performance. In this work, we emphasize the impact of the substrate / BOX interface space charge conditions on the Drain Induced Barrier Lowering (DIBL) increase with gate length reduction, as this drastically changes the channel position in the film and the drain coupling with the channel via substrate and through the BOX. Several modifications to the MASTAR DIBL model are proposed based on ATLAS simulations of the studied structures, in order to explain those effects and fit the experimental data.

Towards the limits of cascaded reversible (quantum-inspired) circuits

Several prototypes and proofs of concept of reversible (quantum-inspired) digital circuits have been successfully realized these last years, proving that digital reversible dual-line pass-transistor technology may be used for reversible linear computations. In order for this new technology to be used in commercial applications, several questions have to be answerd first. In particular, the number of gates possibly cascaded, the maximum reachable frequency, the maximum acceptable delays and amplitude drops are the key issues discussed in this paper.

Interfacing reversible pass-transistor CMOS chips with conventional restoring CMOS circuits

Recent progress on the prototyping of reversible digital circuits, have shown that adiabatic reversible dual-line pass-transistor logic can be used for special purpose applications in reversible computation. This, however, raises new issues regarding the compatibility between this adiabatic logic implementation and conventional CMOS logic. The greatest difficulty is brought by the difference in signal shape used by these two logic families. Whereas standard switching CMOS circuits are operated by rectangular pulses, dual-line pass-transistor reversible circuits are controlled by triangular or trapezoidal signals to ensure adiabatic switching of the transistors. This work proposes a simple technical solution that allows interfacing reversible pass-transistor logic with conventional CMOS logic, represented here by an FPGA embedded in a commercial Xilinx Spartan-3E board. All proposed solutions have successfully been tested, which enables the FPGA to perform calculations directly on a reversible chip.

Designing Garbage-Free Reversible Implementations of the Integer Cosine Transform

Discrete linear transformations are important tools in information processing. Many such transforms are injective and therefore prime candidates for a physically reversible implementation into hardware. We present here reversible integer cosine transformations on <i>n</i> input integers. The resulting reversible circuit is able to perform both the forward transform and the inverse transform. The detailed structure of such a reversible design strongly depends on the odd prime factors of the determinant of the transform: whether those are of the form 2^<i>k</i> ± 1 or of the form 2^<i>k</i> ± 2^<i>l</i> ± 1 or neither of these forms.

Energy Consumption by Reversible ircuits in the 130 nm and 65 nm Nodes

As previous studies in the CMOS 350 nm technology node showed, adiabatic dual-line passtransistor reversible CMOS circuits may be of real interest, especially for human-machine interaction applications such as video, sound and all embedded functions where low-power, low-consumption are mandatory and where frequencies are not the main concern. But the question of viability, suitability and consumption of the quantum-inspired adiabatic reversible CMOS technology with the reduction of the feature size is often asked. With the reduction of transistor sizes, comes an increase of gate leakage that may have a negative impact both on the computation reliability and on the consumption. In another hand, size reduction may allow a gain in performance for an equivalent energy consumption. This paper gives a first evaluation on the consumption by the adiabatic reversible circuit in the 130 nm and 65 nm technology nodes. We show that both 130 nm and 65 nm technologies are suitable for reversible computation. Even better, compared to longer transistor nodes, both small sizes allow to reduce the energy consumption bellow 1 pJ per transistor and per cycle.

A technology based complexity model for reversible Cuccaro ripple-carry adder

Quantum computing and circuits are of growing interest and so is reversible logic as it plays an important role in the synthesis of quantum circuits. Moreover, reversible logic provides an alternative to classical computing machines, that may overcome many of the power dissipation problems in the near future. In effect, the applied adiabatic signals are known to allow the signal energy stored on the various capacitances of the circuit to be redistributed rather than being dissipated as heat. They additionally avoid calculation errors introduced by the use of conventional rectangular pulses. Some ripple-carry adders based on a do-spy-undo structure have been designed and tested reversibly. This paper presents a simple complexity model taking into account some physical aspects of the technology, from the study of a cascade of Cuccaro adders processed in standard 0.35 mC MOS technology and used in true reversible calculation (computations being performed forwards and backwards such that addition and subtraction are made reversibly with the same chip), through both, simulations and experimental results. This paper provides a simple physical complexity model as basis for future cost models.