C. Reita

Numerical analysis of poly-TFTs under off conditions

Abstract Polycrystalline silicon thin-film transistors (poly-TFTs) are getting increasingly important for applications in active-matrix flat-panel displays (AMFPDs) and, more generally, for large-area electronics. As the leakage current requirements of poly-TFTs for large area applications become more stringent, it is important to improve our understanding of the physical effects which originate it. The purpose of this work is that of investigating the anomalous behaviour of leakage-currents in poly-TFTs by numerical simulation, taking into account the effect of energy-distributed traps and field-enhanced generation mechanisms. In what follows, we show that the off current is due to the concomitant effects of Poole-Frenkel, trap-assisted and band-to-band tunneling generation mechanisms, and that each of them may be important at different temperature and bias conditions.

Anomalous off-current mechanisms in N-channel poly-Si thin film transistors

Abstract The anomalous off-current (I off ) in polysilicon thin film transistors (polysilicon TFTs) is one of the major problems preventing a wide use of these devices in active matrix liquid crystal displays. While previous investigations have focused on the temperature range above 300 K, in this study we have investigated the behaviour of I off over a wide range of temperatures, namely 180–400 K. The data have been analysed by combining 2D simulations and existing analytic models. By this approach we have identified a pure trap-to-band tunnelling mechanism in polysilicon TFTs and deduced, by a simple procedure, the physical constants. The temperature and bias dependence of the off-current has been explained quantitatively in terms of phonon-assisted tunnelling. The number of generating centres, the dominant trap energy and the thermal capture cross section are deduced from this analysis.

Off-current in polycrystalline silicon thin film transistors : an analysis of the thermally generated component

Abstract The thermal generation component of polycrystalline silicon TFTs off-current is analysed experimentally and theoretically. In order to minimize the field-enhanced component of the leakage current, hot-hole injection, obtained by stressing the device at negative gate voltage and high source-drain voltage, has been used to reduce the electric field at the drain junction. After stress, the electrical characteristics in the off-regime are channel length independent and do not depend on gate voltage. This behaviour has been associated with the thermal generation-recombination processes occurring at the drain junction. Two-dimensional numerical simulations have been carried out with the program HFIELD, which has been modified to take into account the presence of gap states in polysilicon, and to incorporate the thermal generation-recombination processes by using the Shockley-Read-Hall statistics. Numerical simulations confirm that the generation occurs in the depletion region of the drain junction. The experimental I d - V ds characteristics measured at negative gate voltage have been compared with the calculated characteristics. The best fit with the experimental data was obtained only by using a rather short carrier lifetime (10 −12 s). The simulations indicate that a decrease of the density of states produces a lower off-current owing to a longer carrier lifetime and to a reduction of the drain junction depletion layer.

Analysis of electrical characteristics of polycrystalline silicon thin-film transistors under static and dynamic conditions

Abstract Polycrystalline silicon TFT technology is rapidly emerging for large-area electronic applications, because of the relatively large mobility values of charge carriers with respect to the corresponding values in amorphous silicon. In contrast, because of the complex energy distribution of localized states within the energy gap, and the resulting space-charge effects, the TFT electrical characteristics are difficult to model, and a numerical approach is needed in order to better understand the physical effects which influence the device performances. In this article we perform numerical simulations of TFTs at different temperatures under static and dynamic conditions and, by fitting experimental data, extract the energy distribution and the capture cross-section of the grain-boundary traps and the parameters of the impact-ionization model. As opposed to single-crystal silicon SOI devices, we find that the TFT current and transconductance increase as temperature increases.

Design, measurement and analysis of CMOS polysilicon TFT operational amplifiers

The small signal properties of polysilicon TFT opamps have been investigated in this paper. A method for the scaling of g/sub m/ (transconductance) and g/sub ds/ (output conductance) has been proposed, facilitating their estimates for various transistors in operational amplifiers. The analysis of two CMOS opamps fabricated by a low temperature, glass compatible poly-Si TFT process is demonstrated in comparison to the measured performance. The first implementation has been internally compensated with high load-driving capability (up to 36 pF), while the second one has employed a cascode stage for increased gain (56 dB). >

Hot carriers effects in polycrystalline silicon thin-film transistors

The application of bias-stress with high source-drain voltage and negative gate voltage (transistor in off-status) produces a marked reduction in the off-current as well as a transconductance degradation. These effects have been explained in terms of hotholes injection into the gate insulator and formation of interface states near the drain.

Fabrication and Performance of Digital and Analogue Poly-Si TFT Circuits on Glass

Digital and analogue circuits based on polysilicon thin film transistors (poly-Si TFTs) have been designed and fabricated on glass by a low temperature (≪650 C) process. CMOS shift registers and logic circuitry for integrated drivers for AMLCDs and various types of operational amplifier have been fabricated and tested.