C. Rinn Cleavelin

ESD Evaluation of the Emerging MuGFET Technology

ESD characteristics of fully depleted (FD) FinFET devices are presented and compared to planar structures manufactured in the same multiple-gate FET (MuGFET) technology. FinFET-type MOS devices in breakdown mode are found to show an unprecedented sensitivity to ESD stress, while planar devices and FinFET gated diodes perform reasonably and with I-V characteristics beneficial for ESD protection.

MuGFET carrier mobility and velocity: Impacts of fin aspect ratio, orientation and stress

A detailed study of the impacts of fin aspect ratio and crystalline orientation and process-induced channel stress on the performance of multi-gate transistors is presented. It is found that CESL-induced stress provides for the greatest enhancement in effective carrier mobility and ballistic velocity, for n- and p-channel FinFETs and Tri-Gate FETs. Extracted carrier velocity values in short-channel FinFETs still depend largely on carrier mobility.

FinFET Performance Enhancement with Tensile Metal Gates and Strained Silicon on Insulator (sSOI) Substrate

1. Texas Instruments Inc., SiTD, 13121 TI Boulevard, Dallas, TX USA 2. Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 3. Infineon Technologies, Am Campeon 1-12, 85579 Neubiberg, Germany 4. SOITEC S.A., Parc Technologique des Fontaines 38190 Bernin, France 5. Synopsys, Inc., 700 E. Middlefield Road, Mountain View, CA 94043 USA Phone: (510) 643-2639 Fax: (510) 643-2636, E-mail: ksshinweecs.berkeley.edu

Impact of Gate-Induced Strain on MuGFET Reliability

Hot carrier injection (HCI) reliability and negative bias temperature instability (NBTI) of multiple-gate field-effect transistors (MuGFETs) with highly tensile metal gate electrodes were investigated. The results were compared with those from control devices with poly-Si gate electrodes. It was found that gate strain boosts performance without any detrimental effect on HCI or NBTI reliability, indicating MuGFET compatibility with strained silicon technology. The impact of fin width (W fin) scaling was also investigated. HCI reliability improves with W fin scaling, whereas NBTI reliability degrades with W fin scaling. The same W fin scaling trends were observed in both strained and unstrained devices.

Multigate SOI MOSFETs: Accumulation-mode vs. enhancement-mode

The performances of accumulation-mode and inversion-mode multigate FETs are compared. Both simulation and experimental data are presented. Accumulation-mode devices have a higher current drive and less process variability than inversion-mode FETs.

Ring Oscillator Performance and Parasitic Extraction Simulation in Finfet Technology

Correlation of a full parasitic extracted simulation using StarRC and SPICE to silicon is demonstrated for fully depleted (FD) FinFET silicon-on-insulator ring oscillators. The results indicate similar accuracy can be expected as obtained from bulk simulations. This is important in integrated circuit development, as the accurate simulation of circuit performance is imperative to IC development

A merged MuGFET and planar SOI process

Tri-gate MuGFET (Multi-Gate FET) offers advantages compared to bulk silicon, with respect to circuit design, but also has some potential drawbacks in thermal effects and width quantization. An advantage of MuGFET is that with the same processing it is possible to make planar SOI structures, which, depending upon the active silicon thickness, may be fully or partially depleted. This work investigates circuit operation on a merged MuGFET and planar SOI process.

Comparison of short channel effect between SOI and sSOI triple-gate MOSFETs.

The multiple gate MOSFETs transistors such as double-, triple-, and quadruple-gate MOSFETs on siliconon-insulator (SOI) substrate become the key devices for advanced CMOS technology because of their high performance and tolerance of short-channel effect (SCE) [1-4]. Furthermore, strained-SOI (sSOI) techniques, which utilize the mobility improvement, have been widely studied to overcome the current limitation. [5, 6] To compare short channel and coupling effects between triple-gate MOSFET fabricated on SOI and sSOI substrate, triple-gate MOSFETs were fabricated with same geometrical factors such as fin width of 15 nm, fin height of 60 nm, and fin numbers of 20 and spliting gate lengths from 10 um to 85 nm. Fig. 1 shows the variation of threshold voltage as a function of gate length in n-channel triple-gate MOSFETs fabricated on SOI and sSOI substrate. The triple-gate sSOI MOSFETs exhibit earlier threshold voltage roll-off than that of triple-gate SOI MOSFETs, which explains that the low effective mass and the narrow band-gap due to tensile stress induced from the sSOI substrate increases the junction and gate tunneling leakage current and hence enhances the SCE. Fig. 2 shows the off-current leakage and the onand off-current ratios for both SOI and sSOI triple-gate MOSFET. The off-current leakage current of sSOI device at Vg = 0 are almost 10 times higher than that of SOI device. High off-current leakage of sSOI device decreases the onand off-current ratio. Due to above reasons, the subthreshold slope of sSOI device is also higher than that of SOI device as shown in Fig. 3. Stronger short channel effect in sSOI device reflects higher coupling effect for the device, exhibiting a larger coupling coefficient as shown in Fig. 4. We have studied the short channel effect of triplegate MOSFETs fabricated on both SOI and sSOI substrate. The results showed that the sSOI devices exhibit poor SCE properties compared to SOI devices, such as rapid threshold voltage roll-off, large off-current leakage and strong coupling effect, which are believed to be mainly due to narrow bang-gap and low effective mass.