Rick L. Wise

Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing

Semiconductor industry has increasingly resorted to strain as a means of realizing the required node-to-node transistor performance improvements. Straining silicon fundamentally changes the mechanical, electrical (band structure and mobility), and chemical (diffusion and activation) properties. As silicon is strained and subjected to high-temperature thermal processing, it undergoes mechanical deformations that create defects, which may significantly limit yield. Engineers have to manipulate these properties of silicon to balance the performance gains against defect generation. This paper will elucidate the current understanding and ongoing published efforts on all these critical properties in bulk strained silicon. The manifestation of these properties in CMOS transistor performance and designs that successfully harness strain is reviewed in the last section. Current manufacturable strained-silicon technologies are reviewed with particular emphasis on scalability. A detailed case study on recessed silicon germanium transistors illustrates the application of the fundamentals to optimal transistor design.

Improvement of FinFET electrical characteristics by hydrogen annealing

Hydrogen anneal is used during FinFET processing to round off the corners of the silicon fins prior to gate oxidation and to smooth the surface of the fin sidewalls. This procedure greatly improves gate leakage and, in addition, reduces the width of the fins, resulting in a lower threshold voltage and improved drain-induced barrier lowering (DIBL) characteristics. Reduction of the leakage current by up to four orders of magnitude is obtained after edge rounding by hydrogen annealing. In addition, a 50% decrease of DIBL is observed, due to fin width reduction.

TCAD Simulation of Hot-Carrier and Thermal Degradation in STI-LDMOS Transistors

Physically based models of hot-carrier stress and dielectric-field-enhanced thermal damage have been incorporated into a TCAD tool with the aim of investigating the electrical degradation in integrated power devices over an extended range of stress biases and ambient temperatures. An analytical formulation of the distribution function accounting for the effects of the full band structure has been employed for hot-carrier modeling purposes. A quantitative understanding of the kinetics and local distribution of degradation is achieved, and the drift of the most relevant parameters is nicely predicted on an extended range of stress times and biases.

Physics-Based Analytical Model for HCS Degradation in STI-LDMOS Transistors

A physics-based analytical model for the on-resistance in the linear transport regime and its application as an alternative tool for the investigation of the hot-carrier stress degradation in shallow-trench-isolation-based laterally diffused MOS devices are presented. The extraction of the model and its validation by comparison with experimental and TCAD data are reported. A thorough investigation of the degradation under low- and high-gate stress biases, corresponding to saturation and impact-ionization regimes, is carried out to gain an insight on the overall bias and temperature dependences of the parameter drifts.

Probing nanoscale local lattice strains in advanced Si complementary metal-oxide-semiconductor devices

Local lattice strains in nanoscale Si complementary metal-oxide-semiconductor (MOS) transistors are directly measured by convergent beam electron diffraction (CBED). Through both high spatial resolution and high strain sensitivity of the CBED technique, compressive strains on the order of 10−3 from a p-type MOS transistor with a sub-100nm gate length are detected. One-dimensional quantitative strain mapping is demonstrated. The tensile strains from a ⟨100⟩ channel n-type MOS transistor are observed at the ⟨910⟩ zone axis. It is found that the strain increases with the thickness of the silicon nitride-capping layer, which is consistent with the device’s electrical behavior.

Effective Modulation of Quadratic Voltage Coefficient of Capacitance in MIM Capacitors Using

We report the first demonstration of metal-insulator-metal (MIM) capacitors with Sm₂O₃/SiO₂ stacked dielectrics for precision analog circuit applications. By using the ldquocanceling effectrdquo of the positive quadratic voltage coefficient of capacitance (VCC) of Sm₂O₃ and the negative quadratic VCC of SiO₂, MIM capacitors with capacitance density exceeding 7.3 fF/mum², quadratic VCC of around -50 ppm/V², and leakage current density of 1 times 10^-7 A/cm² at +3.3 V are successfully demonstrated. The obtained capacitance density and quadratic VCC satisfy the technical requirements specified in the International Technology Roadmap for Semiconductors through the year 2013 for MIM capacitors to be used in precision analog circuit applications.

\hbox{Sm}_{2}\hbox{O}_{3}/\hbox{SiO}_{2}

The influence of chip layout and architecture on the pattern dependency of selective epitaxy of B-doped SiGe layers has been studied. The variations of Ge-, B-content, and growth rate have been investigated locally within a wafer and globally from wafer to wafer. The results are described by the gas depletion theory. Methods to control the variation of layer profile are suggested.

Dielectric Stack

This study presents investigations about the physical mechanisms, origin, and methods to control the pattern dependency in selective epitaxial growth of Si1-xGex (x=0.14-0.32) layers. It is shown ...

Comprehensive Evaluation and Study of Pattern Dependency Behavior in Selective Epitaxial Growth of B-Doped SiGe Layers

Strained-Si/relaxed-Si/sub 1-x/Ge/sub x/ structures provide a viable means of improving CMOS performance. For nMOS devices, the tensile strain in pseudomorphic Si on relaxed-Si/sub 1-x/Ge/sub x/ splits the six-fold degeneracy of the conduction band minimum, rendering increased electron mobility due to a lower in-plane effective mass and reduced intervalley scattering. In this paper, in addition to confirming enhanced performance for biaxial-strained-Si nMOS, we present hot-electron degradation characteristics for the first time, showing improvement over bulk Si.

Pattern dependency in selective epitaxy of B-doped SiGe layers for advanced metal oxide semiconductor field effect transistors

We report the first demonstration of metal-insulator-metal (MIM) capacitors with Sm₂O₃/SiO₂ laminated dielectrics featuring low quadratic voltage coefficient of capacitance (VCC) and high capacitance density for precision analog circuit applications. In comparison with a HfO₂ MIM dielectric, the Sm₂O₃ MIM dielectric is found to show a smaller quadratic VCC and a similar dielectric constant. We also investigated the cancellation of the positive quadratic VCC of Sm₂O₃ through its combination with a SiO₂ layer having a negative quadratic VCC. Thus, MIM capacitors with a Sm₂O₃/SiO₂ laminated dielectric were fabricated with various Sm₂O₃ and SiO₂ thickness combinations. Capacitors with the Sm₂O₃/SiO₂ laminated dielectric exhibit tunable quadratic VCC and high capacitance density. Very low quadratic VCC at various capacitance densities were achieved. The leakage current mechanism is related to Poole-Frenkel emission at a high positive bias. A smaller quadratic VCC is obtained at higher frequencies. We also conducted an extensive physical characterization of Sm₂O₃ using transmission electron microscopy, X-ray diffraction, and X-ray photoelectron spectroscopy.