C. Schulte-Braucks

Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications

Guided by the Wentzel-Kramers-Brillouin approximation for band-to-band tunneling (BTBT), various performance boosters for Si TFETs are presented and experimentally verified. Along this line, improvements achieved by the implementation of uniaxial strain in nanowires (NW), the benefits of high-k/metal gates, and newly engineered tunneling junctions as well as the effect of scaling the NW to diameters of 10 nm are demonstrated. Specifically, self-aligned ion implantation into the source/drain silicide and dopant segregation has been exploited to achieve steep tunneling junctions with less defects. The obtained devices deliver high on-currents, e.g., gate-all-around (GAA) NW p-TFETs with 10 nm diameter show ID = 64 μA/μm at VDS = VGS - Voff = -1.0 V, and good inverse subthreshold slopes (SS). Tri-gate TFETs reach minimum SS of 30 mV/dec. Dopant segregation helps to minimize the defect density in the junction and thus trap assisted tunneling (TAT) is reduced. Pulsed current-voltage (I-V) measurements have been used to investigate TAT. We could show that scaled NW devices with multigates are less vulnerable to TAT compared to planar devices due to a shorter tunneling path enabled by the inherently good electrostatics. Furthermore, SiGe NW homo- and heterojunction TFETs have been investigated. The advantages of a SiGe/Si heterostructure as compared to a homojunction device are revealed and the effect of line tunneling which results in an increased BTBT generation is demonstrated. It is also shown that complementary strained Si TFET inverters and p-TFET NAND gates can be operated at VDD as low as 0.2 V. This suggests a great potential of TFETs for ultralow power applications. The analysis of GAA NW TFETs for analog applications provided a high transconductance efficiency and large intrinsic gain, even higher than for state-of-the-art 20 nm FinFETs at low voltages.

Negative differential resistance in direct bandgap GeSn p-i-n structures

Certain GeSn alloys are group IV direct bandgap semiconductors with prospects for electrical and optoelectronical applications. In this letter, we report on the temperature dependence of the electrical characteristics of high Sn-content Ge0.89Sn0.11 p-i-n diodes. NiGeSn contacts were used to minimize the access resistance and ensure compatibility with silicon technology. The major emphasis is placed on the negative differential resistance in which peak to valley current ratios up to 2.3 were obtained. TCAD simulations were performed to identify the origin of the various current contributions, providing evidence for direct band to band tunneling and trap assisted tunneling.

Low Temperature Deposition of High-k/Metal Gate Stacks on High-Sn Content (Si)GeSn-Alloys

(Si)GeSn is an emerging group IV alloy system offering new exciting properties, with great potential for low power electronics due to the fundamental direct band gap and prospects as high mobility material. In this Article, we present a systematic study of HfO2/TaN high-k/metal gate stacks on (Si)GeSn ternary alloys and low temperature processes for large scale integration of Sn based alloys. Our investigations indicate that SiGeSn ternaries show enhanced thermal stability compared to GeSn binaries, allowing the use of the existing Si technology. Despite the multielemental interface and large Sn content of up to 14 atom %, the HfO2/(Si)GeSn capacitors show small frequency dispersion and stretch-out. The formed TaN/HfO2/(Si)GeSn capacitors present a low leakage current of 2 × 10(-8) A/cm(2) at -1 V and a high breakdown field of ∼8 MV/cm. For large Sn content SiGeSn/GeSn direct band gap heterostructures, process temperatures below 350 °C are required for integration. We developed an atomic vapor deposition process for TaN metal gate on HfO2 high-k dielectric and validated it by resistivity as well as temperature and frequency dependent capacitance-voltage measurements of capacitors on SiGeSn and GeSn. The densities of interface traps are deduced to be in the low 10(12) cm(-2) eV(-1) range and do not depend on the Sn-concentration. The new processes developed here are compatible with (Si)GeSn integration in large scale applications.

Novel SiGe/Si line tunneling TFET with high Ion at low Vdd and constant SS

This paper presents a novel SiGe/Si tunneling field-effect transistor (TFET) which exploits line tunneling parallel with the gate electric field. The device makes use of selective and self-adjusted silicidation and a counter doped pocket within the SiGe layer at the source tunnel junction, resulting in a high on-current Ion = 6.7 μA/μm at a supply voltage VDD = -0.5 V and a constant subthreshold swing (SS) of about 80 mV/dec over four orders of magnitude of drain-current Id.

Performance benchmarking of p-type In 0.65 Ga 0.35 As/GaAs 0.4 Sb 0.6 and Ge/Ge 0.93 Sn 0.07 hetero-junction tunnel FETs

We experimentally demonstrate and benchmark the performance of p-channel TFETs (PTFETs) comparing Group III-V (In<inf>0.65</inf>Ga<inf>0.35</inf>As/GaAs<inf>0.4</inf>SW<inf>0.6</inf>) against Group IV (Ge/Ge<inf>0.93</inf>Sn<inf>0.07</inf>) semiconductor hetero-junctions. This is enabled via gate stack engineering with extremely scaled dielectrics achieving the highest accumulation capacitance density (≥3μF/cm²) on both GaAs<inf>0.4</inf>Sb<inf>0.6</inf> and Ge<inf>0.88</inf>Sn<inf>0.12</inf> channels, respectively. Temperature and electric field dependent I-V measurements coupled with first-principles density functional theory (DFT) based band-structure calculations and analytical modeling based on modified Shockley-Read-Hall formalism, are used to quantify contributions to carrier transport from band-to-band tunneling and trap-assisted tunneling (TAT). GeSn based PTFETs are found to outperform In<inf>0.65</inf>Ga<inf>0.35</inf>As/GaAs<inf>0.4</inf>Sb<inf>0.6</inf> PTFETs benefiting from band-gap engineering (higher I<inf>on</inf>) and reduced phonon assisted TAT current (lower D<inf>it</inf>).

Experimental demonstration of improved analog device performance in GAA-NW-TFETs

We present experimental data on analog device performance of p-type planar and gate all around (GAA) nanowire (NW) Tunnel-FETs (TFETs). 10 nm diameter GAA-NW-TFETs reach a maximum transconductance efficiency of 12.7V-1 which is close to values obtained from simulations. A significant improvement of the analog performance by enhancing the electrostatics from planar TFETs to GAA-NW-TFETs with diameter of 20 nm and 10 nm is demonstrated. A maximum transconductance of 122 μS/μm and on-current up to 23 μ A/μm at a gate overdrive of Vgt = Vd = -1 V were achieved for the GAA-NW-TFETs. Furthermore a good output current-saturation is observed leading to high intrinsic gain up to 217 which is even higher than in 20 nm FinFETs.

Line Tunneling Dominating Charge Transport in SiGe/Si Heterostructure TFETs

This paper provides an experimental proof that both the ON-current ION and the subthreshold swing SS of Si(Ge)-based tunneling FETs (TFETs) drastically benefit from device architectures promoting line tunneling aligned with the gate electrical field. A novel SiGe/Si heterostructure TFET is fabricated, making use of a selective and self-adjusted silicidation, thus enlarging the area for band-to-band-tunneling (BTBT) in a region directly underneath the gate. In addition, a counter-doped pocket within the SiGe layer at the source tunnel junction is introduced in order to sharpen the corresponding doping profile and, consequently, to shorten the resulting tunneling length. Experimental analysis of activation energies Eα identifies BTBT, dominating the drain current Id in the SiGe/Si heterostructure TFET over a wide region of the gate voltage Vg, thus reducing parasitic influence of Shockley-Read-Hall recombination and trap-assisted tunneling. Both a relatively high ION = 6.7 μA/μm at a supply voltage VDD = 0.5 V and an average SS of about 80 mV/decade over four orders of magnitude of Id were achieved.

Schottky barrier tuning via dopant segregation in NiGeSn-GeSn contacts

We present a comprehensive study on the formation and tuning of the Schottky barrier of NiGeSn metallic alloys on Ge1-xSnx semiconductors. First, the Ni metallization of GeSn is investigated for a wide range of Sn contents (x = 0–0.125). Structural analysis reveals the existence of different poly-crystalline NiGeSn and Ni3(GeSn)5 phases depending on the Sn content. Electrical measurements confirm a low NiGeSn sheet resistance of 12 Ω/□ almost independent of the Sn content. We extracted from Schottky barrier height measurements in NiGeSn/GeSn/NiGeSn metal-semiconductor-metal diodes Schottky barriers for the holes below 0.15 eV. They decrease with the Sn content, thereby confirming NiGeSn as an ideal metal alloy for p-type contacts. Dopant segregation for both p- and n-type dopants is investigated as a technique to effectively modify the Schottky barrier of NiGeSn/GeSn contacts. Secondary ion mass spectroscopy is employed to analyze dopant segregation and reveal its dependence on both the Sn content and bia...

Correlation of bandgap reduction with inversion response in (Si)GeSn/high-k/metal stacks.

The bandgap tunability of (Si)GeSn group IV semiconductors opens a new era in Si-technology. Depending on the Si/Sn contents, direct and indirect bandgaps in the range of 0.4-0.8 eV can be obtained, offering a broad spectrum of both photonic and low power electronic applications. In this work, we systematically studied capacitance-voltage characteristics of high-k/metal gate stacks formed on GeSn and SiGeSn alloys with Sn-contents ranging from 0 to 14 at. % and Si-contents from 0 to 10 at. % particularly focusing on the minority carrier inversion response. A clear correlation between the Sn-induced shrinkage of the bandgap energy and enhanced minority carrier response was confirmed using temperature and frequency dependent capacitance voltage-measurements, in good agreement with k.p theory predictions and photoluminescence measurements of the analyzed epilayers as reported earlier. The enhanced minority generation rate for higher Sn-contents can be firmly linked to the bandgap reduction in the GeSn epilayer without significant influence of substrate/interface effects. It thus offers a unique possibility to analyze intrinsic defects in (Si)GeSn epilayers. The extracted dominant defect level for minority carrier inversion lies approximately 0.4 eV above the valence band edge in the studied Sn-content range (0-12.5 at. %). This finding is of critical importance since it shows that the presence of Sn by itself does not impair the minority carrier lifetime. Therefore, the continuous improvement of (Si)GeSn material quality should yield longer nonradiative recombination times which are required for the fabrication of efficient light detectors and to obtain room temperature lasing action.

Current mirrors with strained Si single nanowire gate all around Schottky barrier MOSFETs

In this work, we present a simple current mirror based on two single nanowire strained silicon Schottky barrier (SB) MOSFETs with gate-all-around (GAA) structure. B+ implantation into NiSi2 with dopant segregation at source and drain was used to decrease the Schottky barrier height for holes at the metal/channel junctions. The current mirror shows a very good Mirror Ratio MR = 0.99 and high output resistance of 100MΩ.