Stephan Wirths

Ballistic One-Dimensional InAs Nanowire Cross-Junction Interconnects

Coherent interconnection of quantum bits remains an ongoing challenge in quantum information technology. Envisioned hardware to achieve this goal is based on semiconductor nanowire (NW) circuits, comprising individual NW devices that are linked through ballistic interconnects. However, maintaining the sensitive ballistic conduction and confinement conditions across NW intersections is a nontrivial problem. Here, we go beyond the characterization of a single NW device and demonstrate ballistic one-dimensional (1D) quantum transport in InAs NW cross-junctions, monolithically integrated on Si. Characteristic 1D conductance plateaus are resolved in field-effect measurements across up to four NW-junctions in series. The 1D ballistic transport and sub-band splitting is preserved for both crossing-directions. We show that the 1D modes of a single injection terminal can be distributed into multiple NW branches. We believe that NW cross-junctions are well-suited as cross-directional communication links for the reliable transfer of quantum information as required for quantum computational systems.

Ballistic one-dimensional transport in InAs nanowires monolithically integrated on silicon

We present the monolithic integration and electrical characterization of InAs nanowires (NWs) with the well-defined geometries and positions on Si as a platform for quantum transport studies. Hereby, one-dimensional (1D) ballistic transport with step-like 1D conductance quantization in units of 2e2/h is demonstrated for NWs with the widths between 28u2009nm and 58u2009nm and a height of 40u2009nm. The electric field control of up to four individual modes is achieved. Furthermore, the sub-band structure of the nanowires is investigated using bias spectroscopy. The splitting between the first and the second sub-band increases as the width of the NWs is reduced, whereas the degeneracy of the second sub-band can be tuned by the symmetry of the NW cross section, in accordance with a “particle in a box” model. The length-dependent studies reveal ballistic transport for up to 300u2009nm and quasi-ballistic transport with a mean free path of 470u2009nm for longer InAs NW channels at 30u2009K. We anticipate that the ballistic 1D transpor...

High-Mobility GaSb Nanostructures Cointegrated with InAs on Si

GaSb nanostructures integrated on Si substrates are of high interest for p-type transistors and mid-IR photodetectors. Here, we investigate the metalorganic chemical vapor deposition and properties of GaSb nanostructures monolithically integrated onto silicon-on-insulator wafers using template-assisted selective epitaxy. A high degree of morphological control allows for GaSb nanostructures with critical dimensions down to 20 nm. Detailed investigation of growth parameters reveals that the GaSb growth rate is governed by the desorption processes of an Sb surface layer and, in turn, is insensitive to changes in material transport efficiency. The GaSb crystal structure is typically zinc-blende with a low density of rotational twin defects, and even occasional twin-free structures are observed. Hall/van der Pauw measurements are conducted on 20 nm-thick GaSb nanostructures, revealing high hole mobility of 760 cm2/(V s), which matches literature values for high-quality bulk GaSb crystals. Finally, we demonstrate a process that enables cointegration of GaSb and InAs nanostructures in close vicinity on Si, a preferred material combination ideally suited for high-performance complementary III-V metal-oxide-semiconductor technology.

Monolithic integration of multiple III-V semiconductors on Si for MOSFETs and TFETs

In this paper we report on our work on the monolithic integration of various III-V compounds on Si using template-assisted selective epitaxy (TASE) and its application for electronic devices. Nanowires, crossbar nanostructures, and micron-sized sheets are epitaxially grown on Si via metal-organic chemical vapor deposition and form the basis for III-V MOSFETs and Tunnel FETs. Epitaxy conditions specific to TASE are discussed and material quality assessed. Here, we focus on InAs and GaSb as a potential all-III-V alternative to complementary group IV technology. Scaled n-FETs as well as both n- and p-channel TFETs are fabricated on Si and illustrate the potential of TASE.

Towards Nanowire Tandem Junction Solar Cells on Silicon

The development of photovoltaics as a serious means of producing renewable energy has accelerated greatly in the last ten years, with prices for silicon-based solar cell systems dropping dramatically in the last few years. The next great opportunity for photovoltaics following this competitiveness in prices will be to enhance the cell and panel efficiencies. It is quite generally seen that the most viable platform on which this should be realized will be as augmented silicon solar cells, in which a top cell will be combined with the silicon bottom cell in a tandem configuration, by which the efficiency can be enhanced by a factor from 20% to 50%, depending on details of the approach. In this paper, we report on the status of one such approach, namely, with a top cell comprising III–V nanowires, connected to the bottom silicon cell in a two-terminal or four-terminal configuration. Among the most important opportunities, we show that a substrate-free growth, called Aerotaxy, offers a radical reduction in the total price picture. Besides the description of the key technical approaches, we also discuss the environmental issues.

Room temperature lasing from monolithically integrated gaas microdisks on Si

Additional functionalities on semiconductor microchips are progressively important in order to keep up with the ever increasing demand for more powerful computational systems. Recently, III-V integration on Si attracted significant research interest [1] due to the promise to merge mature Si CMOS processing technology with III-V semiconductors possessing superior material properties e.g. in terms of carrier mobility or band structure (direct band gap). In particular, Si photonics would strongly benefit from an integration scheme for active III-V optoelectronic devices in order to enable low-cost and power-efficient electronic-photonic integrated-circuits. In this regard, tremendous progress was achieved using various integration routes for laser sources including wafer bonding [2], buffer layers [3] or dislocation trapping [4].

Microcavity III-V lasers monolithically grown on silicon

We will present our recent work on III-V micro-cavity lasers monolithically grown on silicon substrates. The III-V material is directly grown using Template-Assisted-Selective-Epitaxy (TASE) within oxide cavities patterned using conventional lithographic techniques on top of the silicon substrate. This allows for the local integration of single-crystal III-V active gain material. Two variations of this technique will be discussed; the direct growth of disc lasers and the two-step approach via a virtual substrate. Room temperature single-mode optically pumped lasing is achieved in GaAs micro-cavity lasers, and devices show a remarkably low shift of the lasing threshold (T0=170K) with temperature. Dependence on cavity geometry and pump power will be discussed.

Dopant-Induced Modifications of GaxIn(1–x)P Nanowire-Based p–n Junctions Monolithically Integrated on Si(111)

Today, silicon is the most used material in photovoltaics, with the maximum conversion efficiency getting very close to the Shockley-Queisser limit for single-junction devices. Integrating silicon with higher band-gap ternary III-V absorbers is the path to increase the conversion efficiency. Here, we report on the first monolithic integration of Ga xIn(1- x)P vertical nanowires, and the associated p-n junctions, on silicon by the Au-free template-assisted selective epitaxy (TASE) method. We demonstrate that TASE allows for a high chemical homogeneity of ternary alloys through the nanowires. We then show the influence of doping on the chemical composition and crystal phase, the latter previously attributed to the role of the contact angle in the liquid phase in the vapor-liquid-solid technique. Finally, the emission of the p-n junction is investigated, revealing a shift in the energy of the intraband levels due to the incorporation of dopants. These results clarify some open questions on the effects of doping on ternary III-V nanowire growth and provide the path toward their integration on the silicon platform in order to apply them in next-generation photovoltaic and optoelectronic devices.

Monolithically integrated III-V gain material on virtual substrates on Si using template-assisted selective epitaxy

Monolithically integrated light sources on silicon are key for future semiconductor microchips that comprise Si CMOS and on-chip optical interconnects as prerequisite for more energy efficient computers and data centres. Recently, major advances were achieved regarding direct integration of III-V gain material on silicon without introducing threading dislocations, especially via heteroepitaxy of semiconductor nanowires [1]. In particular, lasing of III-V nanowires on silicon [2] have been reported demonstrating the high potential of such devices for future on-chip light sources. However, nanowire cavities provide only low optical feedback from the NW-end facets which increases their lasing threshold. Additionally, vertically grown nanowires hinder efficient coupling to in-plane photonic waveguides and circuitries.

Monolithic integration of III-V nanostructures for electronic and photonic applications

We have recently developed a novel III-V integration scheme, where III-V material is grown directly on top of Si within oxide nanotubes or microcavities which control the geometry of nanostructures. This allows us to grow III-V material non-lattice matched on any crystalline orientation of Si, to grow arbitrary shapes as well as abrupt heterojunctions, and to gain more flexibility in tuning of composition. In this talk, applications for electronic devices such as heterojunction tunnel FETs and microcavity III-V lasers monolithically integrated on Si will be discussed along with an outlook for the future.