Asen Asenov

Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness

In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation experiments, we investigate the impact of the rms amplitude /spl Delta/ and the correlation length /spl Lambda/ on the intrinsic parameter fluctuations in well scaled, but simple devices with fixed geometry as well as the channel length and width dependence of the fluctuations at fixed LER parameters. For the first time, we superimpose in the simulations LER and random discrete dopants and investigate their relative contribution to the intrinsic parameter fluctuations in the investigated devices. For particular MOSFET geometries, we were able to identify the regions where each of these two sources of intrinsic parameter fluctuations dominates.

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

Intrinsic parameter fluctuations introduced by discreteness of charge and matter will play an increasingly important role when semiconductor devices are scaled to decananometer and nanometer dimensions in next-generation integrated circuits and systems. In this paper, we review the analytical and the numerical simulation techniques used to study and predict such intrinsic parameters fluctuations. We consider random discrete dopants, trapped charges, atomic-scale interface roughness, and line edge roughness as sources of intrinsic parameter fluctuations. The presented theoretical approach based on Greens functions is restricted to the case of random discrete charges. The numerical simulation approaches based on the drift diffusion approximation with density gradient quantum corrections covers all of the listed sources of fluctuations. The results show that the intrinsic fluctuations in conventional MOSFETs, and later in double gate architectures, will reach levels that will affect the yield and the functionality of the next generation analog and digital circuits unless appropriate changes to the design are made. The future challenges that have to be addressed in order to improve the accuracy and the predictive power of the intrinsic fluctuation simulations are also discussed.

Statistical variability and reliability in nanoscale FinFETs

A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented. Excellent electrostatic integrity and resulting tolerance to low channel doping are perceived as the main FinFET advantages, resulting in a dramatic reduction of statistical variability due to random discrete dopants (RDD). It is found that line edge roughness (LER), metal gate granularity (MGG) and interface trapped charges (ITC) dominate the parameter fluctuations with different distribution features, while RDD may result in relatively rare but significant changes in the device characteristics.

Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations

Intrinsic threshold voltage fluctuations introduced by local oxide thickness variations (OTVs) in deep submicrometer (decanano) MOSFETs are studied using three-dimensional (3-D) numerical simulations on a statistical scale. Quantum mechanical effects are included in the simulations employing the density gradient (DG) formalism. The random Si/SiO/sub 2/ and gate/SiO/sub 2/ interfaces are generated from a power spectrum corresponding to the autocorrelation function of the interface roughness. The impact on the intrinsic threshold voltage fluctuations of both the parameters used to reconstruct the random interface and the MOSFET design parameters are studied using carefully designed simulation experiments. The simulations show that intrinsic threshold voltage fluctuations induced by local OTV become significant when the dimensions of the devices become comparable to the correlation length of the interface. In MOSFETs with characteristic dimensions below 30 nm and conventional architecture, they are comparable to the threshold voltage fluctuations introduced by random discrete dopants.

Design and fabrication of memory devices based on nanoscale polyoxometalate clusters

Flash memory devices—that is, non-volatile computer storage media that can be electrically erased and reprogrammed—are vital for portable electronics, but the scaling down of metal–oxide–semiconductor (MOS) flash memory to sizes of below ten nanometres per data cell presents challenges. Molecules have been proposed to replace MOS flash memory, but they suffer from low electrical conductivity, high resistance, low device yield, and finite thermal stability, limiting their integration into current MOS technologies. Although great advances have been made in the pursuit of molecule-based flash memory, there are a number of significant barriers to the realization of devices using conventional MOS technologies. Here we show that core–shell polyoxometalate (POM) molecules can act as candidate storage nodes for MOS flash memory. Realistic, industry-standard device simulations validate our approach at the nanometre scale, where the device performance is determined mainly by the number of molecules in the storage media and not by their position. To exploit the nature of the core–shell POM clusters, we show, at both the molecular and device level, that embedding [(Se(iv)O3)2]4− as an oxidizable dopant in the cluster core allows the oxidation of the molecule to a [Se(v)2O6]2− moiety containing a {Se(v)–Se(v)} bond (where curly brackets indicate a moiety, not a molecule) and reveals a new 5+ oxidation state for selenium. This new oxidation state can be observed at the device level, resulting in a new type of memory, which we call ‘write-once-erase’. Taken together, these results show that POMs have the potential to be used as a realistic nanoscale flash memory. Also, the configuration of the doped POM core may lead to new types of electrical behaviour. This work suggests a route to the practical integration of configurable molecules in MOS technologies as the lithographic scales approach the molecular limit.

Poly-Si-Gate-Related Variability in Decananometer MOSFETs With Conventional Architecture

In this paper, we present a comprehensive statistical 3-D simulation study of the effect of polysilicon (poly-Si) gate granularity on the threshold voltage variability in decananometer MOSFETs with conventional (bulk) architecture. Initially, the effect of both the pinning of the Fermi level and the doping nonuniformity at the poly-Si grain boundaries are studied and compared considering a single grain boundary crossing through the middle of the channel for different pinning positions and doping concentrations at the boundary. This is followed by systematic simulation results for the impact of the grain-size distribution on the standard deviation of the threshold voltage in a simple 30 30 nm MOSFET with uniform channel doping for different pinning positions and doping levels at the grain boundaries. Finally, simulation results for the magnitude of the threshold voltage variations induced by the poly-Si granularity are presented for a set of carefully scaled ldquorealisticrdquo bulk MOSFETs with gate lengths of 35, 25, 18, 13, and 9 nm and are compared with the variations introduced by random discrete dopants and line-edge roughness.

Si/SiGe heterostructure parameters for device simulations

This paper is based on a comprehensive review of the literature and our own studies. We present a summary of the theoretical models and related empirical expressions to evaluate parameters related to the carrier transport within Si/SiGe heterostructures. The models and expressions include the effects of alloy composition and mechanical strain on the band structure of Si/SiGe alloys and the corresponding interfaces. They are presented in a form suitable for implementation in various types of device simulators. Important parameters, such as the band structure of strained or relaxed SiGe, the conduction and valence band offsets in the Si1−xGex/Si1−yGey heterostructures, the effective transport masses and the densities of states, have been calculated and shown to be in good agreement with existing experimental and theoretical results. Analytical expressions of those parameters as a function of Ge composition of the SiGe alloy have been given for strained Si on relaxed Si1−yGey substrate and strained Si1−xGex on Si substrate.

A Self-Consistent Full 3-D Real-Space NEGF Simulator for Studying Nonperturbative Effects in Nano-MOSFETs

In this paper, we present a full 3-D real-space quantum-transport simulator based on the Greens function formalism developed to study nonperturbative effects in ballistic nanotransistors. The nonequilibrium Green function (NEGF) equations in the effective mass approximation are discretized using the control-volume approach and solved self-consistently with the Poisson equation in order to obtain the electron and current densities. An efficient recursive algorithm is used in order to avoid the computation of the full Green function matrix. This algorithm, and the parallelization scheme used for the energy cycle, allow us to compute very efficiently the current-voltage characteristic without the simplifying assumptions often used in other quantum-transport simulations. We have applied our simulator to study the effect of surface roughness and stray charge on the ID-VG characteristic of a 6-nm Si-nanowire transistor. The results highlight the distinctly 3-D character of the electron transport, which cannot be accurately captured by using 1-D and 2-D NEGF simulations, or 3-D mode-space approximations.

Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study

This paper presents a comprehensive full-scale three-dimensional simulation scaling study of the statistical threshold-voltage variability in bulk high-k/metal gate (HKMG) MOSFETs with gate lengths of 35, 25, 18, and 13 nm. Metal gate granularity (MGG) and corresponding workfunction-induced threshold-voltage variability have become important sources of statistical variability in bulk HKMG MOSFETs. It is found that the number of metal grains covering the gate plays an important role in determining the shape of the threshold-voltage distribution and the magnitude of the threshold-voltage variability in scaled devices in the presence of dominant variability sources (MGG, random discrete dopants, and line edge roughness). The placement of metal grains is found to also contribute to the total MGG variability. This paper presents the relative importance of MGG compared with other statistical variability sources. It is found that MGG can distort and even dominate the threshold-voltage statistical distribution when the metal grain size cannot be adequately controlled.

Simulation of Statistical Variability in Nano MOSFETs

Using 3D statistical numerical simulations we study and compare the impact of various sources of statistical variability in nano-CMOS transistors including random discrete dopants (RDD), line edge roughness (LER), polysilicon granularity (PSG) and interface roughness (IR). We show that the random dopant induced parameter fluctuations in conventional MOSFETs become a showstopper, impacting already adversely on their integration in SRAMs, and may force early transition to UTB SOI and double gate device architectures.