Gareth Roy

Poly-Si-Gate-Related Variability in Decananometer MOSFETs With Conventional Architecture

In this paper, we present a comprehensive statistical 3-D simulation study of the effect of polysilicon (poly-Si) gate granularity on the threshold voltage variability in decananometer MOSFETs with conventional (bulk) architecture. Initially, the effect of both the pinning of the Fermi level and the doping nonuniformity at the poly-Si grain boundaries are studied and compared considering a single grain boundary crossing through the middle of the channel for different pinning positions and doping concentrations at the boundary. This is followed by systematic simulation results for the impact of the grain-size distribution on the standard deviation of the threshold voltage in a simple 30 30 nm MOSFET with uniform channel doping for different pinning positions and doping levels at the grain boundaries. Finally, simulation results for the magnitude of the threshold voltage variations induced by the poly-Si granularity are presented for a set of carefully scaled ldquorealisticrdquo bulk MOSFETs with gate lengths of 35, 25, 18, 13, and 9 nm and are compared with the variations introduced by random discrete dopants and line-edge roughness.

Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study

This paper presents a comprehensive full-scale three-dimensional simulation scaling study of the statistical threshold-voltage variability in bulk high-k/metal gate (HKMG) MOSFETs with gate lengths of 35, 25, 18, and 13 nm. Metal gate granularity (MGG) and corresponding workfunction-induced threshold-voltage variability have become important sources of statistical variability in bulk HKMG MOSFETs. It is found that the number of metal grains covering the gate plays an important role in determining the shape of the threshold-voltage distribution and the magnitude of the threshold-voltage variability in scaled devices in the presence of dominant variability sources (MGG, random discrete dopants, and line edge roughness). The placement of metal grains is found to also contribute to the total MGG variability. This paper presents the relative importance of MGG compared with other statistical variability sources. It is found that MGG can distort and even dominate the threshold-voltage statistical distribution when the metal grain size cannot be adequately controlled.

Random-Dopant-Induced Drain Current Variation in Nano-MOSFETs: A Three-Dimensional Self-Consistent Monte Carlo Simulation Study Using “ Ab Initio ” Ionized Impurity Scattering

A comprehensive simulation study of random-dopant-induced drain current variability is presented for a series of well-scaled n-channel MOSFETs representative of the 90-, 65-, 45-, 35-, and 22-nm technology nodes. Simulations are performed at low and high drain biases using both 3-D drift diffusion (DD) and 3-D Monte Carlo (MC). The ensemble MC simulator incorporates an ldquo ab initiordquo treatment of ionized impurity scattering through the real-space trajectories of the carriers in the Coulomb potential of the random discrete impurities. When compared with DD simulations, the MC simulations reveal a significant increase in the drain current variability as a result of additional transport variations due to position-dependent Coulomb scattering that is not captured within the DD mobility model. Such transport variations are in addition to the electrostatic variation in carrier density that is alone captured within the DD approach. Through comparison of the DD and MC results, we estimate the relative importance of electrostatic and transport-induced variability at different drain bias conditions.

Accurate Statistical Description of Random Dopant-Induced Threshold Voltage Variability

We have studied the detailed threshold voltage distribution in a state-of-the-art n-channel MOSFET in the presence of random discrete dopants. A ground-breaking sample of 100 000 transistors with statistically unique random dopant distributions were simulated using the Glasgow 3-D device simulator and advanced grid computing technologies. The results indicate that the threshold voltage distribution deviates substantially from a Gaussian distribution, which may have significant implications for the margins used in circuit design, particularly in SRAM cells.

Analysis of Threshold Voltage Distribution Due to Random Dopants: A 100 000-Sample 3-D Simulation Study

Using the Glasgow ldquoatomisticrdquo simulator, we have performed 3D statistical simulations of random-dopant-induced threshold voltage variation in state-of-the-art 35- and 13-nm bulk MOSFETs consisting of statistical samples of 105 or more microscopically different transistors. Simulation on such an unprecedented scale has been enabled by grid technology, which allows the distribution and the monitoring of very large ensembles on heterogeneous computational grids, as well as the automated handling of large amounts of output data. The results of these simulations show a pronounced asymmetry in the distribution of the MOSFET threshold voltages, which increases with transistor scaling. A comprehensive statistical analysis enabled by the large sample size reveals the origin of this observed asymmetry, provides a detailed insight into the underlying physical processes, and enables the statistical enhancement of simulations of random-dopant-induced threshold voltage variation.

Simulation Study of Dominant Statistical Variability Sources in 32-nm High-

Comprehensive 3-D simulations have been carried out and compared with experimental data highlighting the dominant sources of statistical variability in 32-nm high-κ/metal gate MOSFET technology. The statistical variability sources include random discrete dopants, line edge roughness, and metal gate granularity. Their relative importance is highlighted in the numerical simulations. Excellent agreement is achieved between the simulated and measured standard deviation of the threshold voltage.

\kappa

The strategy to generate statistical model parameters is essential for variability-aware design. Based on 3D atomistic simulation results, this article evaluates the accuracy of statistical parameter generation for two industry-standard compact device models.

/Metal Gate CMOS

Based on the statistical 3D device simulation of well scaled 25, 18 and 13nm physical gate length bulk MOSFETs, the impact of random dopant fluctuation on 6-T SRAM is studied in detail. The bias control approach is introduced to improve the scalability of bulk CMOS SRAM. Simulation results indicate that at 13nm physical gate length, bulk CMOS SRAM will face fundamental challenges arising from intrinsic parameter fluctuation, and a replacement by ultra thin body SOI CMOS may be necessary at this point

Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP

Increasing CMOS device variability has become one of the most acute problems facing the semiconductor manufacturing and design industries at, and beyond, the 45 nm technology generation. Most problematic of all is the statistical variability introduced by the discreteness of charge and granularity of matter in transistors with features already of molecular dimensions [i]. Two transistors next to each other on the chip with exactly the same geometries and strain distributions may have characteristics from each end of a wide statistical distribution. In conjunction with statistical variability [ii], negative bias temperature instability (NBTI) and/or hot carrier degradation can result in acute statistical reliability problems. It already profoundly affects SRAM design, and in logic circuits causes statistical timing problems and is increasingly leading to hard digital faults. In both cases, statistical variability restricts supply voltage scaling, adding to power dissipation problems [iii]. In this invited paper we describe recent advances in predictive physical simulation of statistical variability using drift diffusion (DD), Monte Carlo (MC) and quantum transport (QT) simulation techniques.

Impact of Random Dopant Fluctuation on Bulk CMOS 6-T SRAM Scaling

In this paper we present a methodology for the integrated atomistic process and device simulation of decananometre MOSFETs. The atomistic process simulations were carried out using the kinetic Monte Carlo process simulator DADOS, which is now integrated into the Synopsys 3D process and device simulation suite Taurus. The device simulations were performed using the Glasgow 3D statistical atomistic simulator, which incorporates density gradient quantum corrections. The overall methodology is illustrated in the atomistic process and device simulation of a well behaved 35 nm physical gate length MOSFET reported by Toshiba.