Cao Yan-Rong

Negative Bias Temperature Instability “Recovery" under Negative Stress Voltage with Different Oxide Thicknesses

Different phenomena are observed under negative gate voltage stress which is smaller than the previous degradation stress in PMOSFETs with different oxide thicknesses. We adopt the real time method to make a point of the drain current to study the degradation and recovery of negative bias temperature instability (NBTI). For the device with thin oxide, recovery phenomenon appears when smaller negative voltage stress was applied, due to the more influencing oxide charges detrapping effects than the interface states. For the device with thick oxide, not recovery but degradation phenomenon comes forth. As many charges are trapped in the deeper position and higher energy level in the oxide, these charges can not be detrapped. Therefore, the effect of the charge detrapping is smaller than that of the interface states in the thick oxide. The degradation presents itself during the ‘recovery’ time.

Effect of Channel Length and Width on NBTI in Ultra Deep Sub-Micron PMOSFETs *

The effects of channel length and width on the degradation of negative bias temperature instability (NBTI) are studied. With the channel length decreasing, the NBTI degradation increases. As the channel edges have more damage and latent damage for the process reasons, the device can be divided into three parts: the gate and source overlap region, the middle channel region, and the gate and drain overlap region. When the NBTI stress is applied, the non-uniform distribution of the generated defects in the three parts will be generated due to the inhomogeneous degradation. With the decreasing channel length, the channel edge regions will take up a larger ratio to the middle channel region and the degradation of NBTI is enhanced. The channel width also plays an important role in the degradation of NBTI. There is an inflection point during the decreasing channel width. There are two particular factors: the lower vertical electric field effect for the thicker gate oxide thickness of the shallow trench isolation (STI) edge and the STI mechanical stress effecting on the NBTI degradation. The former reduces and the latter intensifies the degradation. Under the mutual compromise of the both factors, when the effect of the STI mechanical stress starts to prevail over the lower vertical electric field effect with the channel width decreasing, the inflection point comes into being.

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4 nm) gate oxide is investigated under the low gate voltage stress (LGVS) and peak substrate current (Isub, max) stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage (GIDL) current and stress induced leakage current (SILC). The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub, max stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.

Investigation of the characteristics of GIDL current in 90nm CMOS technology

A specially designed experiment is performed for investigating gate-induced drain leakage (GIDL) current in 90nm CMOS technology using lightly-doped drain (LDD) NMOSFET. This paper shows that the drain bias VD has a strong effect on GIDL current as compared with the gate bias VG at the same drain–gate voltage VDG. It is found that the difference between ID in the off-state ID−VG characteristics and the corresponding one in the off-state ID−VD characteristics, which is defined as IDIFF, versus VDG shows a peak. The difference between the influences of VD and VG on GIDL current is shown quantitatively by IDIFF, especially in 90nm scale. The difference is due to different hole tunnellings. Furthermore, the maximum IDIFF(IDIFF,MAX) varies linearly with VDG in logarithmic coordinates and also VDG at IDIFF,MAX with VF which is the characteristic voltage of IDIFF. The relations are studied and some related expressions are given.

Degradation mechanism of enhancement-mode AlGaN/GaN HEMTs using fluorine ion implantation under the on-state gate overdrive stress*

The degradation mechanism of enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs) fabricated by fluorine plasma ion implantation technology is one major concern of HEMT’s reliability. It is observed that the threshold voltage shows a significant negative shift during the typical long-term on-state gate overdrive stress. The degradation does not originate from the presence of as-grown traps in the AlGaN barrier layer or the generated traps during fluorine ion implantation process. By comparing the relationships between the shift of threshold voltage and the cumulative injected electrons under different stress conditions, a good agreement is observed. It provides direct experimental evidence to support the impact ionization physical model, in which the degradation of E-mode HEMTs under gate overdrive stress can be explained by the ionization of fluorine ions in the AlGaN barrier layer by electrons injected from 2DEG channel. Furthermore, our results show that there are few new traps generated in the AlGaN barrier layer during the gate overdrive stress, and the ionized fluorine ions cannot recapture the electrons.

Electron Trap Energy Distribution in HfO2 by the Discharge-Based Pulse I–V Technique

The electron traps in HfO2 are a major concern of the reliability of metal-oxide-semiconductor field effect transistors (MOSFETs) beyond the 30 nm technology generation. In this work, the principle of the discharge-based pulse I–V technique is demonstrated in detail. By using this technique, the thorough energy distribution of electron traps across the 4 nm HfO2 layer is identified, which overcomes the shortcomings of the current techniques. It is observed that there are two peaks in HfO2. The large peak is at around 1.0 eV below the HfO2 conduction band bottom. The small peak is at about 1.43 eV below the HfO2 conduction band bottom. The results provide valuable information for theoretical modeling establishment, fast material assessment and process optimization for MOSFETs with high-k gate dielectrics.

Degradation of Ultra-Thin Gate Oxide NMOSFETs under CVDT and SHE Stresses ∗

Degradation of device under substrate hot-electron (SHE) and constant voltage direct-tunnelling (CVDT) stresses are studied using NMOSFET with 1.4-nm gate oxides. The degradation of device parameters and the degradation of the stress induced leakage current (SILC) under these two stresses are reported. The emphasis of this paper is on SILC and breakdown of ultra-thin-gate-oxide under these two stresses. SILC increases with stress time and several soft breakdown events occur during direct-tunnelling (DT) stress. During SHE stress, SILC firstly decreases with stress time and suddenly jumps to a high level, and no soft breakdown event is observed. For DT injection, the positive hole trapped in the oxide and hole direct-tunnelling play important roles in the breakdown. For SHE injection, it is because injected hot electrons accelerate the formation of defects and these defects formed by hot electrons induce breakdown.

Effect of gate length on the parameter degradation relations of PMOSFET under NBTI stress

The influence of PMOSFET gate length on the parameter degradation relations under negative bias temperature instability (NBTI) stress is studied. The threshold voltage degradation increases with reducing the gate length. By calculating the relations between the threshold voltage and the linear/saturation drain current, we obtain their correlation coefficients. Comparing the test result with the calculated linear/saturation current value, we obtain the ratio factors. The ratio factors decrease differently when the gate length diminishes. When the gate length reduces to some degree, the linear ratio factor decreases from greater than 1 to nearly 1, but the saturation factor decreases from greater than 1 to smaller than 1. This results from the influence of mobility and the velocity saturation effect. Moreover, due to the un-uniform distribution of potential damages along the channel, the descending slopes of the curve are different.

Degradation of ultra-thin gate oxide LDD NMOSFET under GIDL stress

The degradation of device under GIDL (gate-induced drain leakage current) stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC (stress induced leakage current) in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and Vh degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.