Chen Hai-Feng

Investigation of the characteristics of GIDL current in 90nm CMOS technology

A specially designed experiment is performed for investigating gate-induced drain leakage (GIDL) current in 90nm CMOS technology using lightly-doped drain (LDD) NMOSFET. This paper shows that the drain bias VD has a strong effect on GIDL current as compared with the gate bias VG at the same drain–gate voltage VDG. It is found that the difference between ID in the off-state ID−VG characteristics and the corresponding one in the off-state ID−VD characteristics, which is defined as IDIFF, versus VDG shows a peak. The difference between the influences of VD and VG on GIDL current is shown quantitatively by IDIFF, especially in 90nm scale. The difference is due to different hole tunnellings. Furthermore, the maximum IDIFF(IDIFF,MAX) varies linearly with VDG in logarithmic coordinates and also VDG at IDIFF,MAX with VF which is the characteristic voltage of IDIFF. The relations are studied and some related expressions are given.

Gate-modulated generation—recombination current in n-type metal—oxide—semiconductor field-effect transistor

Gate-modulated generation—recombination (GMGR) current IGMGR induced by the interface traps in an n-type metal—oxide—semiconductor field-effect transistor (nMOSFET) is investigated. The generation current is found to expand rightwards with increasing the reversed drain PN junction bias, and the recombination current is enhanced as the forward drain bias increases. The variations of IGMGR curves are ascribed to the changes of the electron density and hole density at the interface, NS and PS, under the different drain bias voltages. Based on an analysis of the physical mechanism, the IGMGR model is set up by introducing two coefficients (m and t). The coefficients m and t can modulate the curves widths and peak values. The simulated results under reverse mode and forward mode are obviously in agreement with the experimental results. This proves that this model can be applicable for generation current and recombination current and that the theory behind the model is reasonable. The details of the relevant mechanism are given in the paper.

Degradation of the transconductance of a gate-modulated generation current in nMOSFET

The degradation of transconductance (G) of a gate-modulated generation current IGD in a LDD nMOSFET is investigated. The G curve shifts rightward under the single electron-injection-stress (EIS). The trapped electrons located in the gate oxide over the LDD region (QL) makes the effective drain voltage diminish. Accordingly, the G peak in depletion (GMD) and that in weak inversion (GMW) decrease. It is found that ΔGMD and ΔGMW each have a linear relationship with the n-th power of stress time (tn) in a dual-log coordinate: ΔGMD ∝ tn, ΔGMD ∝ tn (n = 0.25). During the alternate stress, the injected holes neutralize QL induced by the previous EIS. This neutralization makes the effective VD restore to the initial value and then the IGD peak recovers completely. Yet the threshold voltage recovery is incomplete due to the trapped electron located over the channel (QC). As a result, GMW only recovers to circa 50% of the initial value after the hole-injection-stress (HIS). Instead, GMD almost recovers. The relevant mechanisms are given in detail.

Characteristics of drain-modulated generation current in n-type metal-oxide-semiconductor field-effect transistor*

Drain-modulated generation current IDMG induced by interface traps in an n-type metal-oxide-semiconductor field-effect transistor (nMOSFET) is investigated. The formation of IDMG ascribes to the change of the Si surface potential s. This change makes the channel suffer transformation from the inversion state, depletion I state to depletion II state. The simulation result agrees with the experiment in the inversion and depletion I states. In the depletion II state, the theoretical curve goes into saturation, while the experimental curve drops quickly as VD increases. The reason for this unconformity is that the drain-to-gate voltage VDG lessens s around the drain corner and controls the falling edge of the IDMG curve. The experiments of gate-modulated generation and recombination currents are also applied to verify the reasonability of the mechanism. Based on this mechanism, a theoretical model of the IDMG falling edge is set up in which IDMG has an exponential attenuation relation with VDG. Finally, the critical fitting coefficient t of the experimental curves is extracted. It is found that t = 80 mV = 3kT/q. This result fully shows the accuracy of the above mechanism.

Effect of substrate negative bias on GIDL current in LDD nMOSFET's

The effect of substrate negative bias V<inf>B</inf> on the gate-induced drain leakage (GIDL) current is studied. It is found that the negative V<inf>B</inf> leads GIDL current curve shifts upwards. The shift of GIDL current ΔI<inf>D</inf>/I<inf>D</inf> increases with increasing |V<inf>B</inf>|. The GIDL current at V<inf>G</inf>=−0.2V (in the low field region) increases with increasing |V<inf>B</inf>| more largely than that at V<inf>G</inf>=−1.2V (in the high field region). This is because that the negative V<inf>B</inf> results in the additional GIDL tunneling current in the lateral direction and it has the different effects on the low field region and high field region. It is also found that ΔI<inf>D</inf>/I<inf>D</inf> at V<inf>D</inf>=0.8V is larger than that at V<inf>D</inf>=0.4V under V<inf>G</inf>=−1.2V and is smaller than that at V<inf>D</inf>=0.4V under V<inf>G</inf>=−0.2V. This ascribes the different roles of the GIDL vertical tunneling current and the GIDL lateral current induced by negative V<inf>B</inf> on the whole GIDL current.

GIDL current degradation in LDD nMOSFET under hot hole stress

The degradation of gate-induced drain leakage (GIDL) current in LDD nMOSFET under hot holes stress is studied in depth based on its parameter IDIFF.IDIFF is the difference of GIDL currents measured under two conditions of drain voltage VD = 1.4 V and gate voltage VG = −1.4 V while VDG is fixed. After the stress GIDL currents decay due to holes trapping in the oxide around the gate-to-drain overlap region. These trapped holes diminish ΔEX which is the deference of the lateral electrical field of these two symmetrical measurement conditions in the overlap region so as to make IDIFF lessening. IDIFF extracted from GIDL currents decreases with increasing stress time t. The degradation shifts of IDIFF,MAX (ΔIDIFF,MAX) follows a power law against t: ΔIDIFF,MAX ∝ tm, m = 0.3. Hot electron stress is performed to validate the related mechanism.

The Anomalous Effect of Interface Traps on Generation Current in Lightly Doped Drain nMOSFET's

The anomalous phenomenon of generation current IGD in the lightly doped drain (LDD) nMOSFET measured under the drain bias VD-step mode is reported. We propose an assumption of activated (A) and frozen (F) traps for the VD-step mode: The A traps contributes to IGD while the F process can make them lose the roles as generation centers. The A and F regions can form the F-A region. The comparison of the F and A regions decides the role of the F-A region. The experiments confirm the assumption.

Comparison of hot-hole injections in ultrashort channel LDD nMOSFETs with ultrathin oxide under an alternating stress

The behaviours of three types of hot-hole injections in ultrashort channel lightly doped drain (LDD) nMOSFETs with ultrathin oxide under an alternating stress have been compared. The three types of hot-hole injections, i.e. low gate voltage hot hole injection (LGVHHI), gate-induced drain leakage induced hot-hole injection (GIDLIHHI) and substrate hot-hole injection (SHHI), have different influences on the devices damaged already by the previous hot electron injection (HEI) because of the different locations of trapping holes and interface states induced by the three types of injections, i.e. three types of stresses. Experimental results show that GIDLIHHI and LGVHHI cannot recover the degradation of electron trapping, but SHHI can. Although SHHI can recover the devices performance, the recovery is slight and reaches saturation quickly, which is suggested here to be attributed to the fact that trapped holes are too few and the equilibrium is reached between the trapping and releasing of holes which can be set up quickly in the ultrathin oxide.

New aspects of HCI test for ultra-short channel n-MOSFET devices

Hot carriers injection (HCI) tests for ultra-short channel n-MOSFET devices were studied. The experimental data of short channel devices (75?90?nm), which does not fit formal degradation power law well, will bring severe error in lifetime prediction. This phenomenon usually happens under high drain voltage (Vd) stress condition. A new model was presented to fit the degradation curve better. It was observed that the peak of the substrate current under low drain voltage stress cannot be found in ultra-short channel device. Devices with different channel lengths were studied under different Vd stresses in order to understand the relations between peak of substrate current (Isub) and channel length/stress voltage.