Hu Shigang

A bootstrapped switch employing a new clock feed-through compensation technique

Nonlinearity caused by the clock feed-through of a bootstrapped switch and its compensation techniques are analyzed. All kinds of clock feed-through compensation configurations and their drawbacks are also investigated. It is pointed out that the delay path match of the clock boosting circuit is the critical factor that affects the effectiveness of clock feed-through compensation. Based on that, a new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with the UMC mixed-mode/RF 0.18 μm 1P6M P-sub twin-well CMOS process by orientating and elaborately designing the switch MOSFETs that influence the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feed-through compensation configuration can not only enhance the sampling accuracy under variations of process, power supply voltage, temperature and capacitors but also decrease the even harmonic, high-order odd harmonic and THD on the whole effectively.

An X-band GaN combined solid-state power amplifier

Based on a self-developed AlGaN/GaN HEMT with 2.5 mm gate width technology on a SiC substrate, an X-band GaN combined solid-state power amplifier module is fabricated. The module consists of an AlGaN/GaN HEMT, Wilkinson power couplers, DC-bias circuit and microstrip line. For each amplifier, we use a bipolar DC power source. Special RC networks at the input and output and a resistor between the DC power source and the gate of the transistor at the input are used for cancellation of self-oscillation and crosstalk of low-frequency of each amplifier. At the same time, branches of length 3λ/4 for Wilkinson power couplers are designed for the elimination of self-oscillation of the two amplifiers. Microstrip stub lines are used for input matching and output matching. Under Vds = 27 V, Vgs = –4.0 V, CW operating conditions at 8 GHz, the amplifier module exhibits a line gain of 5.6 dB with power added efficiency of 23.4%, and output power of 41.46 dBm (14 W), and the power gain compression is 3 dB. Between 8 and 8.5 GHz, the variation of output power is less than 1.5 dB.

An X-band four-way combined GaN solid-state power amplifier

An X-band four-way combined GaN solid-state power amplifier module is fabricated based on a self-developed AlGaN/GaN HEMT with 2.5-mm gate width technology on SiC substrate. The module consists of an AlGaN/GaN HEMT, Wilkinson power hybrids, a DC-bias circuit and microstrip matching circuits. For the stability of the amplifier module, special RC networks at the input and output, a resistor between the DC power supply and a transistor gate at the input and 3λ/4 Wilkinson power hybrids are used for the cancellation of low frequency self-oscillation and crosstalk of each amplifier. Under Vds = 27 V, Vgs = −4.0 V, CW operating conditions at 8 GHz, the amplifier module exhibits a line gain of 5 dB with a power added efficiency of 17.9%, and an output power of 42.93 dBm; the power gain compression is 2 dB. For a four-way combined solid-state amplifier, the power combining efficiency is 67.5%. It is concluded that the reduction in combining efficiency results from the non-identical GaN HMET, the loss of the hybrid coupler and the circuit fabricating errors of each one-way amplifier.

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4 nm) gate oxide is investigated under the low gate voltage stress (LGVS) and peak substrate current (Isub, max) stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage (GIDL) current and stress induced leakage current (SILC). The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub, max stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.

Characteristics and parameter extraction for NiGe/n-type Ge Schottky diode with variable annealing temperatures

Current transport mechanism in Ni-germanide/n-type Ge Schottky diodes is investigated using current–voltage characterisation technique with annealing temperatures from 300 °C to 500 °C. Based on the current transport model, a simple method to extract parameters of the NiGe/Ge diode is presented by using the I–V characteristics. Parameters of NiGe/n-type Ge Schottky diodes fabricated for testing in this paper are as follows: the ideality factor n, the series resistance Rs, the zero-field barrier height b0, the interface state density Dit, and the interfacial layer capacitance Ci. It is found that the ideality factor n of the diode increases with the increase of annealing temperature. As the temperature increases, the interface defects from the sputtering damage and the penetration of metallic states into the Ge energy gap are passivated, thus improving the junction quality. However, the undesirable crystallisations of Ni-germanide are observed together with NiGe at a temperature higher than 400 °C. Depositing a very thin (~1 nm) heavily Ge-doped n+ Ge intermediate layer can improve the NiGe film morphology significantly.

Degradation of Ultra-Thin Gate Oxide NMOSFETs under CVDT and SHE Stresses ∗

Degradation of device under substrate hot-electron (SHE) and constant voltage direct-tunnelling (CVDT) stresses are studied using NMOSFET with 1.4-nm gate oxides. The degradation of device parameters and the degradation of the stress induced leakage current (SILC) under these two stresses are reported. The emphasis of this paper is on SILC and breakdown of ultra-thin-gate-oxide under these two stresses. SILC increases with stress time and several soft breakdown events occur during direct-tunnelling (DT) stress. During SHE stress, SILC firstly decreases with stress time and suddenly jumps to a high level, and no soft breakdown event is observed. For DT injection, the positive hole trapped in the oxide and hole direct-tunnelling play important roles in the breakdown. For SHE injection, it is because injected hot electrons accelerate the formation of defects and these defects formed by hot electrons induce breakdown.

Degradation of ultra-thin gate oxide LDD NMOSFET under GIDL stress

The degradation of device under GIDL (gate-induced drain leakage current) stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC (stress induced leakage current) in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and Vh degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.

Effect of substrate bias on negative bias temperature instability of ultra-deep sub-micro p-channel metal-oxide-semiconductor field-effect transistors

The effect of substrate bias on the degradation during applying a negative bias temperature (NBT) stress is studied in this paper. With a smaller gate voltage stress applied, the degradation of negative bias temperature instability (NBTI) is enhanced, and there comes forth an inflexion point. The degradation pace turns larger when the substrate bias is higher than the inflexion point. The substrate hot holes can be injected into oxide and generate additional oxide traps, inducing an inflexion phenomenon. When a constant substrate bias stress is applied, as the gate voltage stress increases, an inflexion comes into being also. The higher gate voltage causes the electrons to tunnel into the substrate from the poly, thereby generating the electron–hole pairs by impact ionization. The holes generated by impact ionization and the holes from the substrate all can be accelerated to high energies by the substrate bias. More additional oxide traps can be produced, and correspondingly, the degradation is strengthened by the substrate bias. The results of the alternate stress experiment show that the interface traps generated by the hot holes cannot be annealed, which is different from those generated by common holes.

Mechanism of NBTI Recovery under Negative Voltage Stress

Recovery phenomenon is observed under negative gate voltage stress which is smaller than the previous degradation stress. We focus on the drain current to study the degradation and recovery of negative bias temperature instability (NBTI) with a real-time method. By this method, different recovery phenomena among different size devices are observed. Under negative recovery stress, the drain current gradually recovers for the large size devices and gets into recovery saturation when long recovery time is involved. For small-size devices, a step-like recovery of drain current is observed. The recovery of the drain current is mainly caused by the holes detrapping and tunnelling back to the channel surface which are trapped in oxide. The model of hole detrapping explains the recovery under negative voltage stress reasonably.