Carl Barnhart

OPMISR: the foundation for compressed ATPG vectors

Rapid increases in the wire-able gate counts of ASICs stress existing manufacturing test equipment in terms of test data volume and test capacity. Techniques are presented in this paper that allow for substantial compression of Automatic Test Pattern Generation (ATPG) produced test vectors. We show compression efficiencies allowing a more than 10-fold reduction in tester scan buffer data volume on ATPG compacted tests. In addition, we obtain almost a 2/spl times/ scan test time reduction. By implementing these techniques for production testing of huge-gate-count ASICs, IBM will continue using existing automated test equipment (ATE)-avoiding costly upgrades and replacements.

A SmartBIST variant with guaranteed encoding

SmartBIST is a name for a family of streaming scan test pattern decoders that are suitable for on-chip integration. The automatic test pattern generation (ATPG) algorithms are modified to generate scan test stimulus vectors in a highly compacted source format that is compatible with the SmartBIST decoder hardware. The compacted stimulus vectors are streamed from automatic test equipment (ATE) to the decoder, which expands the data stream in real-time into fully expanded scan test vectors. SmartBIST encoding and decoding use simple algebraic techniques similar to those used for LFSR-coding (also known as LFSR-reseeding). The specific SmartBIST implementation shown in this paper guarantees that all test cubes can be successfully encoded by the modified ATPG algorithm irrespective of the number and position of the care bits.

Extending OPMISR beyond 10/spl times/ scan test efficiency

Rapidly increasing ASIC gate counts are stressing the test capacity of manufacturing test equipment. New on-product multiple-input signature register (OPMISR) techniques compress test vectors produced by ATPG, substantially reducing data volume and test time.

IEEE 1149.6: a boundary-scan standard for advanced digital networks

AC-coupled high-speed differential signals have been a hole in the IEEE 1149.1 boundary-scan standard since its inception. In May 2001, a group formed to address this problem, resulting in the IEEE 1149.6 standard. Several members of the IEEE 1149.6 working group describe how the standard works and how it can test Gigabit Ethernet, Fibre Channel and more.

IEEE P1149.6: a boundary-scan standard for advanced digital networks

Very high-speed, digital technology is imposing new requirements on test logic that will limit the effectiveness of current IEEE 1149.1 based testing. IEEE P1149.6 is an extension to IEEE 1149.1 that attempts to standardize the boundary-scan structures and methods required to ensure simple, robust and minimally intrusive boundary-scan testing of advanced digital networks which are not adequately addressed by existing standards. This includes AC-coupled networks, differential networks or both. This paper will describe the work that has been done thus far by the P1149.6 working group including: defects to be targeted by the proposed standard, physical layer implementation for both the driver and receiver, verification of proposed solutions through SPICE modeling, BSDL and tools implications. The paper will also discuss some of the challenges faced by the working group and will discuss new approaches taken on by the working group in the development of the proposed standard.

Status of IEEE testability standards 1149.4, 1532 and 1149.6

Single board, and now multi-board testability is highly conditioned by the availability of various forms of boundary scan technology. This paper surveys the three more recent IEEE Standards relating to boundary scan. The paper is based on three backgrounders prepared by members of the individual Working Groups for the IEEE Standards booth at ITC 2003.

Testing Differential Signals

Virtually all test challenges come down to a matter of controlability and observability. In order to properly test a differential signal, the IEEE 1149.1 standard recommends separate control and observation boundary cells on each leg, creating two single ended nets with full testability. In this model, the differential driver and receiver are part of the functional logic. In most cases, this has an unacceptable impact on functional performance.