Donald L. Wheater

A SmartBIST variant with guaranteed encoding

SmartBIST is a name for a family of streaming scan test pattern decoders that are suitable for on-chip integration. The automatic test pattern generation (ATPG) algorithms are modified to generate scan test stimulus vectors in a highly compacted source format that is compatible with the SmartBIST decoder hardware. The compacted stimulus vectors are streamed from automatic test equipment (ATE) to the decoder, which expands the data stream in real-time into fully expanded scan test vectors. SmartBIST encoding and decoding use simple algebraic techniques similar to those used for LFSR-coding (also known as LFSR-reseeding). The specific SmartBIST implementation shown in this paper guarantees that all test cubes can be successfully encoded by the modified ATPG algorithm irrespective of the number and position of the care bits.

Low-cost testing of high-density logic components

The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBMs high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The testers design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in each component design, built-in self-test logic within embedded memory arrays, and the use of weighted random-pattern logic testing. The development of the tester hardware is discussed, and capital costs of the new tester are compared with those of other approaches. >

Low cost testing of high density logic components

The authors describe the evolution and architecture of a logic device tester for the next generation of high-density logic components to be produced by IBM at its Essex Junction, Vermont, facility. The tester architecture is based on the design of an existing internal memory tester, rather than on the design of a conventional logic tester. This design point was an evolutionary outcome of a comprehensive logic test strategy development process. That strategy called for inclusion of boundary scan and array built-in self test in each component design, and for adoption of weighted random pattern logic testing (WRPT). WRPT enables tester data volumes to be reduced by two orders of magnitude in comparison with stored pattern logic testing, while simultaneously maintaining high test quality. The resulting tester architecture and design are described in the context of those decisions.<<ETX>>The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBMs high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The testers design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in each component design, built-in self-test logic within embedded memory arrays, and the use of weighted random-pattern logic testing. The development of the tester hardware is discussed, and capital costs of the new tester are compared with those of other approaches.<<ETX>>

An on-chip self-repair calculation and fusing methodology

Laser fusing is a standard technique for improving yield with memory reconfiguration and repair, but implementing fusing in production can be challenging and costly. This article introduces an electrically programmable polysilicon fuse and shows how it can reduce fuse area and programming complexity.

On-chip repair and an ATE independent fusing methodology

This paper describes a novel on chip repair system designed for ATE independent application on many unique very dense ASIC devices in a high turnover environment. During test, the system controls on chip built-in self-test (BIST) engines, collects and compresses repair data, programs fuses and finally decompresses and reloads the repair data for post fuse testing. In end use applications this system decompresses and loads the repair data at power-up or at the request of the system.

ASIC test cost/strategy trade-offs

Supplying cost effective testing for large application specific integrated circuits (ASICs) is one of the key challenges facing the semiconductor industry. Projections suggest that it will not be cost effective to continue in the current test direction. ASIC suppliers must be able to offer a flexible, cost-effective set of test solutions that will meet a variety of customer requirements. This paper presents some of the trade-offs used in developing optimal test strategies.

Ate-customer perspectives & requirements panel

Does one do the “minimum” DFT just to avoid buying the “next” tester, does one do all the test “on chip” and cost reduce the ATE down to a battery and a data source and sink, or is silicon so precious that any use for non mission related function make the cost of the final die prohibitive. One can easily find proponents for each position and the data to back it up. This is because the answer is highly dependent on the particulars of the design of the device and the issues related to the business case that the device is going into.