Carlo Kosik Williams

Ultrathin Si Thin-Film Transistor on Glass

We have studied the fabrication of ultrathin single-crystalline-silicon thin-film transistors (TFTs) on glass. The single-crystalline Si layer was transferred to glass by hydrogen implantation and anodic bonding. The thickness of the silicon-on-glass (SiOG) was controlled down to 10 nm by dry etching. The p-channel SiOG TFTs with 10-nm-thick Si exhibited the field-effect mobility of 134.9 cm2/Vmiddots, threshold voltage of -1.5 V, and gate voltage swing of 0.13 V/dec. The TFTs were found to be stable against gate bias stress of +30 or -30 V.

Single Fermi Level Thin-Film CMOS on Glass: The Behavior of Enhancement-Mode PMOSFETs From Cutoff Through Accumulation

A device model which describes the behavior of thin-film transistors fabricated in crystalline silicon on glass is introduced. The dc current-voltage characteristics of fully depleted thin-film silicon p-channel enhancement-mode MOSFETs operated in accumulation is provided. Physically derived expressions are presented for drain current in the accumulation and depletion regions which include the correct dependence on drain voltage, film thickness, and doping level. AC-infin model is realized from cutoff to accumulation by using an interpolant around the flatband voltage and a hyperbolic tangent blending function. The device model shows excellent agreement with measured results for output, transfer, and transconductance characteristics. A compact circuit simulation model has also been implemented in the Spectre circuit simulator using Verilog-A.

P-197L: Late-News Poster: Demonstration of High Performance TFTs on Silicon-on-Glass (SiOG) Substrate

This report is an introduction to a new silicon-on-glass (SiOG) substrate and device technology. The fabrication and analysis of CMOS devices fabricated using SiOG are presented. The SiOG devices are comparable to those fabricated on SOI wafers with respect to carrier mobility and off-state leakage current. This technology clearly demonstrates the potential for system-on-panel integration.

Process development of CdTe solar cells grown at high temperatures on engineered glass

NREL and Corning Incorporated have collaborated on a project to investigate the effect of increasing CdTe deposition temperature on device performance. CdTe deposition temperatures are generally limited by the thermal properties of the glass superstrate. Soda-lime glass is frequently used in commercial production of CdTe, but the low strain point (~515°C) requires deposition temperatures of 550°C or below. While the CdTe industry has enjoyed great success with material grown at these relatively low temperatures, there may be significant benefits to higher deposition temperatures enabled by a high strain point glass. To demonstrate the efficiency benefits of a CdTe cell fabricated at higher deposition temperatures, it is necessary to re-optimize the device fabrication process steps for devices made with CdTe films at each deposition temperature. Using Corning, Inc.s new engineered high-strain-point glass superstrate, we developed a fabrication process optimized for CdTe films deposited at 550° and 600°C. Here, we report details of the fabrication processes that resulted in an absolute efficiency gain of 1.2% for devices fabricated with 600°C CdTe deposition temperature versus 550°C.

Effect of annealing atmosphere and temperature on the properties of Cd 2 SnO 4 thin films

Cadmium stannate (Cd₂SnO₄, CTO) thin films were prepared by radio frequency (RF) magnetron sputtering deposition followed by annealing at 550~650°C in Ar, air, Ar/4% H₂ and Ar/CdS at atmospheric pressure. The crystallization onset of the amorphous as-deposited CTO thin films occurs at 550°C, with highly crystallized single phase Cd₂SnO₄ obtained at 600°C and above. Electron mobility increases with the annealing temperature (T_A) and reaches mobilities of ~70, ~69 and ~56 cm²V^-1s^-1 for samples annealed at 650°C in air, Ar and Ar/CdS respectively. Although the samples annealed in Ar/CdS shows relatively lower mobility, the high carrier density ~6.6×1020 cm^-3 (annealed at 650°C) leads to a very low resistivity ~1.7×10^-4 Ω cm and a high optical bandgap ~3.6 eV due to Moss-Burstein shift. The resistivity of the samples annealed in air or Ar is limited by much lower carrier density.

Time-resolved, nonequilibrium carrier dynamics in Si-on-glass thin films for photovoltaic cells

Here, a femtosecond pump–probe spectroscopy method was used to characterize the growth process and transport properties of amorphous silicon-on-glass, thin films, intended as absorbers for photovoltaic cells. We collected normalized transmissivity change (ΔT/T) waveforms and interpreted them using a comprehensive three-rate equation electron trapping and recombination model. Optically excited ~300–500 nm thick Si films exhibited a bi-exponential carrier relaxation with the characteristic times varying from picoseconds to nanoseconds depending on the film growth process. From our comprehensive trapping model, we could determine that for doped and intrinsic films with very low hydrogen dilution the dominant relaxation mode was carrier trapping; while for intrinsic films with large hydrogen content and some texture, it was the standard electron–phonon cooling. In both cases, the initial nonequilibrium relaxation was followed by Shockley–Read–Hall recombination. An excellent fit between the model and the ΔT/T experimental transients was obtained and a correlation between the Si film growth process, its hydrogen content, and the associated trap concentration was demonstrated.

A Charge Based Compact Modeling Technique for Monocrystalline TFTs on Glass

A thin-film monocrystalline CMOS display technology has been realized by implementing a conventional NMOS inversion device and a PMOS accumulation device. In this paper, a charge based modeling technique is introduced which provides the dc currentvoltage characteristics for both inversion and accumulation devices. Since conduction occurs at the surface and in the bulk of accumulation devices, traditional charge sheet models are invalid. Starting directly from the Pao-Sah equation by applying the 1-D Gauss’ Law, C-∞ expressions able to capture the effect of both surface and bulk conduction suitable for circuit simulations are derived. The model is validated against the two-dimensional device simulation.

Boron and Phosphorus Implantation Induced Electrically Active Defects in p-Type Silicon

Electrically active defects induced by ion implantation of boron and phosphorus into silicon and their recovery under isothermal annealing at 450 °C were investigated using Deep Level Transient Spectroscopy (DLTS) and Energy Resolved Tunneling Photoconductivity (ERTP) spectroscopy at cryogenic temperatures. DLTS results show electrically active deep traps located at Ev+0.35 eV and Ev+0.53 eV in boron implanted Si and at Ev+0.34 eV, Ev+0.43 eV, and Ev+0.38 eV in phosphorus implanted Si. These meta-stable defect sites were found to be either eliminated or significantly reduced in thermally annealed samples. We assigned these defect sites to hydrogen and carbon incorporated complexes formed during ion implantation. Corroborating the DLTS results, the photocurrent measurement also revealed a strong reduction of electrically active defects states, extended from EC – 0.3 eV up to the conduction band edge of Si, upon isothermal annealing.

High Field Induced Stress Suppression of GIDL Effects in Accumulation-Mode P-Channel TFTs

By utilizing the effects of high energy, or “hot”, electrons the GIDL current in an accumulation mode thin-film PFET can be suppressed. Both SOI and single crystal silicon-on-glass (SiOG) substrates were used to examine this effect. This suppression is proposed to be due to local injection of charge into the gate-oxide at the drain end of the transistor creating a mirror charge in the silicon which mimics an asymmetrical lightly-doped drain structure. An overview of theory, modeling, and device characterization is presented in this study. This effect has been shown to be stable and reproducible; a technique to measure the location and quantity of injected charge is under development.

Fringing Field Effects in Thin-Film Silicon Transistors on Glass

A new process enabling the transfer of a single-crystal silicon film to a glass substrate has been developed allowing for the creation of fully crystalline thin-film silicon-on-glass (SiOG) transistors. The dominant 2-D effect in SiOG transistors results from fringing electric field lines emanating through the glass substrate between the source, drain, and thin-film channel regions. The fringing field leads to a shift in the flatband or threshold voltage in a similar manner to drain-induced barrier lowering. The fringing field effect can lead to an 11% shift in flatband for devices with channel length of 4 μm and a nominal flatband of -1 V. A compact model for the fringing field in these devices has been developed using conformal mapping techniques that capture the dependence on both channel length and the relative size of the source and drain electrodes. The model accurately predicts the influence of the fringing field on subthreshold drain current for SiOG PFETs operating in accumulation. The model is validated against the 2-D device simulator Silvaco Atlas.