Eric J. Mozdy

Self-referencing a single waveguide grating sensor in a micron-sized deep flow chamber for label-free biomolecular binding assays

In order to allow the design of increasingly sensitive label-free biosensors, compensation of environmental fluctuations is emerging as the dominant hurdle. The system and technique presented here utilize a unique combination of microfluidics, optical instrumentation, and image processing to provide a reference signal for each label-free biomolecular binding assay. Moreover, this reference signal is generated from the same sensor used to detect the biomolecular binding events. In this manner, the reference signal and the binding signal share nearly all common-mode noise sources (temperature, pressure, vibration, etc.) and their subtraction leaves the purest binding signal possible. Computational fluid dynamic simulations have been used to validate the flow behavior and thermal characteristics of the fluids inside the sensing region. This system has been demonstrated in simple bulk refractive index tests, as well as small molecule (biotin/streptavidin) binding experiments. The ability to perform not only simple binding but also control experiments has been discussed, indicating the wide applicability of the technique.

Degradation Model of Self-Heating Effects in Silicon-on-Glass TFTs

This paper investigates the origin and reduction of self-heating effects in single-crystal silicon-on-glass (SiOG) thin-film transistors (TFTs). A hump forms in the transfer characteristics of p-channel SiOG TFTs when the temperature of the devices is increased either by direct heating or electrical biasing. The size of the hump proportionally scales with the channel width W, indicating that it is related to the bulk active-layer properties such as conduction through a backchannel. While the hump increases in the positive direction, the main transistor shifts in the negative direction with increasing self-heating stress time, supporting the exclusion of edge effects. The time dependence of the hump shift is well described by the stretched-exponential behavior, indicating that the backchannel is a result of electron trapping into the silica layer that is between the glass and silicon active layer. To mitigate this hump effect, we demonstrate in this paper that TFTs with an active layer divided into smaller parts along the W direction (in order to increase heat dissipation) show better stability to self-heating stress (i.e., no hump formation) than TFTs with full active layers. Split devices have more channel edges, compared with those with a full active layer, supporting the idea that the hump is indeed not due to edge effects.

Toward film-silicon solar cells on display glass

We describe recent progress in developing epitaxial film crystal silicon (c-Si) solar cells that can be grown at low temperature (<760 °C) on seed-on-glass substrates. This low-cost approach is enabled by rapid epitaxy (up to 300 nm/min) of Si films with low dislocation density (< 1×105 cm⁻²) at glass-compatible temperatures by hot-wire chemical vapor deposition (HWCVD). Epitaxial test cells on heavily-doped ‘dead’ Si wafers provide insight into the quality of the Si absorber and the physics that limit device performance. Our best 2–3 µm thick, film silicon heterojunction (c-Si/a-Si) solar cells have reached ∼6.7% efficiency (V<inf>oc</inf> ∼ 570 mV, J<inf>sc</inf> ∼18 mA/cm⁻²) without rapid thermal anneal, defect passivation or light trapping. Unpassivated dislocations are strong recombination centers and limit effective minority carrier diffusion lengths to less than 15–20 µm (roughly half the distance between dislocations). We also report devices without light-trapping on layer-transfer Si seed layers bonded to display-glass; these seed layers template growth of high-quality HWCVD cSi. Our initial devices have V<inf>oc</inf> = 460 mV, J<inf>sc</inf> = 16.2 mA/cm², Eff. = 4.8 %, but will benefit from post-growth anneals, hydrogenation and new surface treatments before epitaxy. We discuss junction transport physics in the devices and explore the role of post-growth H-passivation and rapid thermal annealing treatments on device performance.

Reduction of Hot Carrier Effects in Silicon-on-Glass TFTs

Hot carrier (HC) instability of thin-film transistors (TFTs) fabricated on single-crystal,silicon-on-glass (SiOG) substrates is studied. The formation of the SiOG substrate is achieved by the transfer of a single-crystal silicon film to a display-glass substrate. The transfer process creates an in-situ barrier layer free of mobile ions in the glass adjacent the silicon film. The n- and p-channel TFT transfer characteristics typically exhibit excellent on-state performance with gate voltage swing values of 180 mV/decade, electron and hole mobilities of ∼251 and 201 cm2/V·s respectively, and threshold voltages of approximately ―0.3 and ―1.2 V for the n- and p-channet TFTs respectively. While p-channel TFTs exhibit good stability, on-current degradation is observed in the transfer characteristics of the n-channel TFT. The degradation is due to HC stress. In this study, the integration of a lightly doped drain (LDD) structure in the n-channel SiOG TFTs to minimize HC instability is reported. The LDD design incorporates 2 μm offset regions. The offset regions are lightly doped (n-) with phosphorus ions implanted at 10 keV. N-levels of ∼ 1 x 1013, 2 x 1013, and 3 x 1013 cm―2 are analyzed to determine the optimum doping conditions that reduce HC instability while minimizing degradation in the on-state device performance.

Low Voltage Driven CMOS Circuits Based on Silicon on Glass

Low voltage driven inverter, ring oscillator and shift registor circuits using n- and p- channel TFTs based on Corning® Siliconon-Glass (SiOG) substrates are studied. The field effect mobility of n- and p-channel TFTs fabricated in SiOG are 226 and 165 cm 2 /V·s, respectively. The TFTs exhibited symmetric threshold voltages of ± 1.1 V and gate voltage swings of 0.21 ~ 0.23 V/dec. The total propagation delay time of the CMOS inverter was 2.54 ns at a supply voltage of 7 V. In addition, the rise and fall times of the shift register were found to be 0.5 µs and 0.7 µs at a VDD of 7 V, respectively. This work demonstrates the the ability to realize high performance integrated CMOS circuits on SiOG substrates.