Carlos Leong

The Clear-PEM Electronics System

The Clear-PEM detector system is a compact positron emission mammography scanner with about 12000 channels aiming at high sensitivity and good spatial resolution. Front-end, Trigger, and Data Acquisition electronics are crucial components of this system. The on-detector front-end is implemented as a data-driven synchronous system that identifies and selects the analog signals whose energy is above a predefined threshold. The off-detector trigger logic uses digitized front-end data streams to compute pulse amplitudes and timing. Based on this information it generates a coincidence trigger signal that is used to initiate the conditioning and transfer of the relevant data to the data acquisition computer. To minimize dead-time, the data acquisition electronics makes extensive use of pipeline processing structures and derandomizer memories with multievent capacity. The system operates at 100-MHz clock frequency, and is capable of sustaining a data acquisition rate of 1 million events per second with an efficiency above 95%, at a total single photon background rate of 10 MHz. The basic component of the front-end system is a low-noise amplifier-multiplexer chip presently under development. The off-detector system is designed around a dual-bus crate backplane for fast intercommunication between the system boards. The trigger and data acquisition logic is implemented in large FPGAs with 4 million gates. Monte Carlo simulation results evaluating the trigger performance, as well as results of hardware simulations are presented, showing the correctness of the design and the implementation approach

Design and test issues of a FPGA based data acquisition system for medical imaging using PEM

The main aspects of the design and test (D&T) of a reconfigurable architecture for the data acquisition electronics (DAE) system of the clear-PEM detector are presented in this paper. The application focuses medical imaging using a compact PEM (positron emission mammography) detector with 12288 channels, targeting high sensitivity and spatial resolution. The DAE system processes data that comes from a front-end (FE) electronics that identifies the relevant data and transfers it to a PC for image processing. The design is supported in a novel D&T methodology, in which hierarchy, modularity and parallelism are extensively exploited to improve design and testability features. Parameterization has also been used to improve design flexibility. Nominal frequency is 100 MHz. The DAE must respond to a data acquisition rate of 1 million relevant events (coincidences) per second, under a total single photon background rate in the detector of 10 MHz. Trigger and data acquisition logic is implemented in eight 4-million, one 2-million and one 1-million gate FPGAs (Xilinx Virtex II). Functional built-in self test (BIST) and debug features are incorporated in the design to allow on-board FPGA testing and self-testing during product lifetime

Design and test issues of an FPGA based data acquisition system for medical imaging using PEM

The main aspects of the design and test (D&T) of a reconfigurable architecture for the Data Acquisition Electronics (DAE) system of the Clear-PEM detector are presented in this paper. The application focuses medical imaging using a compact PEM (Positron Emission Mammography) detector with 12288 channels, targeting high sensitivity and spatial resolution. The DAE system processes data frames that come from a front-end (FE) electronics, identifies the relevant data and transfers it to a PC for image processing. The design is supported in a novel D&T methodology, in which hierarchy, modularity and parallelism are extensively exploited to improve design and testability features. Parameterization has also been used to improve design flexibility. Nominal frequency is 100 MHz. The DAE must respond to a data acquisition rate of 1 million relevant events (coincidences) per second, under a total single photon background rate in the detector of 10 MHz. Trigger and data acquisition logic is implemented in eight 4-million, one 2-million and one 1-million gate FPGAs (Xilinx Virtex II). Functional Built-In Self Test (BIST) and Debug features are incorporated in the design to allow on-board FPGA testing and self-testing during product lifetime.

Performance simulation studies of the clear-PEM DAQ/trigger system

The clear-PEM detector is a positron emission mammography scanner based on high-granularity avalanche photodiodes readout with 12 288 channels. The front-end sub-system is instrumented with low-noise 192:2 channel amplifier-multiplexer ASICs and free-running sampling ADCs. The off-detector trigger, implemented in a FPGA based architecture, computes the pulses amplitude and timing required for coincidence validation from the front-end data streams. A high-level C++ simulation tool was developed for data acquisition performance analysis and validated at bit level against FPGA VHDL testbenches. In this work, simulation studies concerning the performance of the on-line/off-line energy and time extraction algorithms and the foreseen detector energy and time resolution are presented. Time calibration, trigger efficiency and ghosting are also discussed

Aging monitoring with local sensors in FPGA-based designs

In nanoscale FPGAs, variability and aging significantly limit performance. In this paper, a novel aging monitoring methodology for FPGA-based designs to mitigate those effects is proposed. Local sensors are embedded in the configured functionality, monitoring critical paths, at production or during product lifetime. No design freeze (slice and routing locked) is required. When sensors observe a users defined time guardband violation, safe operation is endangered and action can be triggered, either to reduce clock frequency or to increase core VDD. Simulation and experimental results are presented, using Spartan 6 boards and vendor tools. The testbench uses a Data Acquisition (DAQ) system with Triple Modular Redundancy (TMR) architecture and a Built-In Self-Test (BIST) infrastructure. It is shown that local sensors will anticipate system failure. Various devices are also used to analyze sensitivity to process variations.

Performance sensor for tolerance and predictive detection of delay-faults

This paper presents the Scout Flip-Flop, a new performance Sensor for toleranCe and predictive detectiOn of delay-faUlTs in synchronous digital circuits. The sensor is based on a new master-slave Flip-Flop (FF), the Scout FF, with built-in functionality to locally (inside the FF) create two distinct guard-band windows: (1) a tolerance window, to increase tolerance to late transitions, making the Scouts master latch transparent during an additional predefined period after the clock trigger; and (2) a detection window, which starts before the clock edge trigger and persists during the tolerance window, to inform that performance and circuit functionality is at risk. When a PVTA (Process, power-supply Voltage, Temperature and Aging) variation occurs, circuit performance is affected and a delay-fault may occur. Hence, the existence of a tolerance window, introduces an extra time-slack by borrowing time from subsequent clock cycles. Moreover, as the predictive-error detection window starts prior to the clock edge trigger, it provides an additional safety margin and may be used to trigger corrective actions before real error occurrence, such as clock frequency reduction. Both tolerance and detection windows are defined by design and are sensitive to performance errors, increasing its size in worst PVTA conditions. Extensive SPICE simulations allowed characterizing the new flip-flop and simulation results are presented for 65nm CMOS technology, using Berkeley Predictive Technology Models (PTM), showing Scouts effectiveness on tolerance and predictive error detection.

Performance Failure Prediction Using Built-In Delay Sensors in FPGAs

The objective of this paper is to propose a performance failure prediction methodology for FPGA-based designs, based on the use of a novel built-in programmable delay sensor. Digital Clock Managers (DCM) is used to fine tune the unsafe observation interval. The design procedure is described, including the constrained placement of some delay sensors. The proposed technique is particularly useful to monitor parametric Process, supply Voltage and Temperature (PVT) and aging-induced variations. It can be used during product lifetime, as a predictive delay fault detection technique, either to avoid unreliable operation, or to guarantee correct functionality with lower power consumption. The usefulness of the proposed technique is demonstrated with part of the data processor of a complex design for a medical imaging system used in PET-based mammography, configured in a Virtex-4 FPGA device (xc4vfx60-11ff1152).

Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems

The purpose of this paper is to present a novel built-in Clock Domain Crossing (CDC) test and diagnosis methodology for Globally Asynchronous, Locally Synchronous (GALS) systems. The methodology allows design and prototype validation, low maintenance and repair costs, and production / lifetime at-speed test. Moreover, high resolution diagnosis is obtained, to identify which device(s) and/or communication channel(s) is (are) faulty. This is not trivial in GALS systems, for which the CDC issue is challenging. The underlying principle of the proposed methodology is to embed a CDC test and diagnosis (CDC T&D) structure in each locally synchronous domain. Complete device-to-device communication channels are tested, including transceivers, buses, and board connectors. Identical test patterns (generated to detect static (stuck-at, shorts and open faults) and dynamic (crosstalk) faults) are used in each FPGA. The proposed CDC T&D methodology is validated in a case study, the acquisition electronics of a complex multi-board, multibus, multi-FPGA (nine Xilinx™ xc2v4000-4bf957) system. Test and validation results are presented.

An overview of the Clear-PEM breast imaging scanner

We present an overview of the Clear-PEM breast imaging scanner. Clear-PEM is a unique dual-head Positron Emission Mammography scanner using APD-based detector modules that are capable of measuring depth-of-interaction (DOI) with a resolution of 2 mm in 20 mm long LYSO:Ce crystals. Such capability leads to an image spatial resolution of 1.2 mm and a high efficiency, foreseeing the detection of 3 mm breast lesions in less than 7 minutes exams. The full system comprises 192 detector modules in a total of 6144 LYSO:Ce crystals and 384 32-pixel APD arrays readout by ASICs with 192 input channels that represents an unprecedented level of integration in PET systems. Throughout the project and besides the detector module, we had developed dedicated Frontend and Data Acquisition electronics, the mechanical design and construction of the detector heads and the robotic gantry, as well as all the software that include calibration (energy, time and DOI), normalization and image reconstruction algorithms. In this work we will discuss the developments and present the commissioning results of the detector before the beginning of the clinical trials program, scheduled for the end of the present year.

Characterization of the Clear-PEM breast imaging scanner performance

We present results on the characterization of the Clear-PEM breast imaging scanner. Clear-PEM is a dual-head Positron Emission Mammography scanner using APD-based detector modules that are capable of measuring depth-of-interaction (DOI) with a resolution of 2 mm in LYSO:Ce crystals. The full system comprises 192 detector modules in a total of 6144 LYSO:Ce crystals and 384 32-pixel APD arrays readout by ASICs with 192 input channels, which represents an unprecedented level of integration in APD-based PET systems. The system includes Frontend and Data Acquisition electronics and a robotic gantry for detector placement and rotation. The software implements calibration (energy, time and DOI), normalization and image reconstruction algorithms. In this work, the scanner main technical characteristics, calibration strategies and the spectrometric performance in a clinical environment are presented. Images obtained with point sources and extended uniform sources are also presented. The first commissioning results show 99.7% active channels. After calibration, the dispersion of the channels absolute gain is 15.3%, which demonstrate that despite the large number of channels the system is rather uniform. The mean energy resolution at 511 keV is 15.9% for all channels, and the mean DOI constant is 5.9%/mm, which is consistent with a 2 mm DOI resolution, or better. The coincidence time resolution at 511 keV, for a energy window between 400 and 600 keV, is 5.2 ns FWHM. The image resolution measured with point sources was found to be of the order of 1.3 mm FWHM. The DOI capability was found to have a strong impact on the image sharpness. Images of extended uniform 68Ge sources, corrected for sensitivity and for the artifacts due detector dead spaces, have good uniformity. First clinical breast images are presented.