Jorge Semião

Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors

This paper presents a new approach on aging sensors for synchronous digital circuits. An adaptive error-prediction flip-flop architecture with built-in aging sensor is proposed, performing on-line monitoring of long-term performance degradation of CMOS digital systems. The main advantage is that the sensors performance degradation works in favor of the predictive error detection. The sensor is out of the signal path. Performance error prediction is implemented by the detection of late transitions at flip-flop data input, caused by aging (namely, due to NBTI), or to physical defects activated by long lifetime operation. Such errors must not occur in safety-critical systems (automotive, health, space). A sensor insertion algorithm is also proposed, to selectively insert them in key locations in the design. Sensors can be always active or at pre-defined states. Simulation results are presented for a balanced pipeline multiplier in 65 nm CMOS technology, using Berkeley Predictive Technology Models (PTM). It is shown that the impact of aging degradation and/or PVT (Process, power supply Voltage and Temperature) variations on the sensor enhance error prediction.

Predictive error detection by on-line aging monitoring

The purpose of this paper is to present a predictive error detection methodology, based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI), or to physical defects activated by long lifetime operation, which may occur in safety-critical systems (automotive, health, space). Error is prevented by detecting critical paths abnormal (but not fatal) propagation delays. A monitoring procedure and a programmable aging sensor are proposed. The sensor is selectively inserted in key locations in the design and can be activated either on users requirement, or at pre-defined situations (e.g., at power-up). The sensor is optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Sensor limitations are analysed. A new sensor architecture and a sensor insertion algorithm are proposed. Simulation results are presented with a ST 65 nm sensor design.

Aging-Aware Power or Frequency Tuning With Predictive Fault Detection

This paper presents a methodology to use global and local performance sensors, allowing the circuits to be optimized for power and/or performance.

Time Management for Low-Power Design of Digital Systems

The implementation of complex functionality in low-power (LP) nano-CMOS technologies must be carried out in the presence of enhanced susceptibility to PVT (Process, power supply Voltage and Temperature) variations. VT variations are environmental or operation-dependent parametric disturbances. Power constraints (in normal and test mode) are critical, especially for high-performance digital systems. Both dynamic and leakage power induce variable (in time and space) thermal maps across the chip. PVT variations lead to timing variations. These should be accommodated without losing performance. Dynamic, on-line time management becomes necessary. The purpose of this paper is to present a VT-aware time management methodology which leads to improved PVT tolerance, without compromising performance or testability. First, the methodology is presented, highlighting its characteristics and limitations. Its underlying principle is to introduce additional tolerance to VT variations, by time borrowing, dynamically controlling the time of the clock edge trigger driving specific memory cells (referred to as critical memory cells, CME). VT variations are locally sensed, and dynamic delay insertion in the clock signal driving CME is performed, using Dynamic Delay Buffer (DDB) cells. Then, methodology automation, using the proprietary DyDA tool, is explained. The methodology is proved to be efficient, even in the presence of process variations. Finally, it is shown that VT tolerance insertion does not necessarily reduce delay fault detection, as multi-V DD or multi-frequency self-test can be used to recover detection capability.

Signal Integrity Enhancement in Digital Circuits

This article proposes a new methodology for enhancing SoC signal integrity without degrading performance in the presence of power-ground voltage transients. The underlying principle is the dynamic adaptation of the clock duty cycle to propagation delay variation along disturbed logic paths. This methodology makes digital circuits more robust to power line fluctuations while maintaining the at-speed clock rate.

Aging monitoring with local sensors in FPGA-based designs

In nanoscale FPGAs, variability and aging significantly limit performance. In this paper, a novel aging monitoring methodology for FPGA-based designs to mitigate those effects is proposed. Local sensors are embedded in the configured functionality, monitoring critical paths, at production or during product lifetime. No design freeze (slice and routing locked) is required. When sensors observe a users defined time guardband violation, safe operation is endangered and action can be triggered, either to reduce clock frequency or to increase core VDD. Simulation and experimental results are presented, using Spartan 6 boards and vendor tools. The testbench uses a Data Acquisition (DAQ) system with Triple Modular Redundancy (TMR) architecture and a Built-In Self-Test (BIST) infrastructure. It is shown that local sensors will anticipate system failure. Various devices are also used to analyze sensitivity to process variations.

Performance sensor for tolerance and predictive detection of delay-faults

This paper presents the Scout Flip-Flop, a new performance Sensor for toleranCe and predictive detectiOn of delay-faUlTs in synchronous digital circuits. The sensor is based on a new master-slave Flip-Flop (FF), the Scout FF, with built-in functionality to locally (inside the FF) create two distinct guard-band windows: (1) a tolerance window, to increase tolerance to late transitions, making the Scouts master latch transparent during an additional predefined period after the clock trigger; and (2) a detection window, which starts before the clock edge trigger and persists during the tolerance window, to inform that performance and circuit functionality is at risk. When a PVTA (Process, power-supply Voltage, Temperature and Aging) variation occurs, circuit performance is affected and a delay-fault may occur. Hence, the existence of a tolerance window, introduces an extra time-slack by borrowing time from subsequent clock cycles. Moreover, as the predictive-error detection window starts prior to the clock edge trigger, it provides an additional safety margin and may be used to trigger corrective actions before real error occurrence, such as clock frequency reduction. Both tolerance and detection windows are defined by design and are sensitive to performance errors, increasing its size in worst PVTA conditions. Extensive SPICE simulations allowed characterizing the new flip-flop and simulation results are presented for 65nm CMOS technology, using Berkeley Predictive Technology Models (PTM), showing Scouts effectiveness on tolerance and predictive error detection.

Design and Validation of Configurable Online Aging Sensors in Nanometer-Scale FPGAs

In current CMOS nanometer technologies, aging effects may appear after relatively short operating times, compared to the expected lifetime of circuits. Therefore, there is an increasing need for on-chip aging monitoring, especially in high-performance, safety critical systems. This paper presents a programmable aging sensor that can be embedded in field-programmable gate array (FPGA)-based designs, using standard resources available in those devices and with minimal impact on the standard FPGA design flow. Given the limited amount of resources required by the sensor, it can be instantiated not only in the critical paths of a circuit, but also in those that may be identified to be more likely affected by aging effects. Experimental results, obtained in circuits of increasing complexity (where several sensors need to be used), are presented and discussed, demonstrating the good performance of the proposed sensor, as well as its low cost in terms of area overhead and power consumption. Results of aging experiments based on the standard US MIL-STD-883 Method 1015.50 “Burn-In Test” are also reported, demonstrating that the effect of aging on the sensor is negligible compared to that on the circuit under test, which is a key point for practical applicability. The proposed approach provides a novel and efficient solution to the specific FPGA design problems in this context, which are different from those addressed in application-specific integrated circuit design.

On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications

Electronic design of high-performance digital systems in nano-scale CMOS technologies under Process, power supply Voltage, Temperature and Aging (PVTA) variations is a challenging process. Such variations induce abnormal timing delays leading to systems errors, harmful in safety-critical applications. Performance Failure Prediction (PFP), instead of error detection, becomes necessary, particularly in the presence of aging effects. In this paper, an on-line BIST methodology for PFP in a standard cell design flow is proposed. The methodology is based on abnormal delay detection associated with critical signal paths. PVTA-aware aging sensors are designed. Multilevel simulation is used. Functional and structural test pattern generation is performed, targeting the detection of critical path delay faults. A sensor insertion technique is proposed, together with an up-graded version of a proprietary software tool, DyDA. Finally, a novel strategy for gate-level Aging fault injection is proposed, using the concept of an Aging de-rating factor. Results are presented for a Serial Parallel Interface (SPI) controller, designed with commercial UMC 130nm CMOS technology and Faraday™ cell library. Only seven sensors are required to monitor unsafe performance operation, due to Negative Bias Thermal Instability (NBTI)-induced aging.

Performance Failure Prediction Using Built-In Delay Sensors in FPGAs

The objective of this paper is to propose a performance failure prediction methodology for FPGA-based designs, based on the use of a novel built-in programmable delay sensor. Digital Clock Managers (DCM) is used to fine tune the unsafe observation interval. The design procedure is described, including the constrained placement of some delay sensors. The proposed technique is particularly useful to monitor parametric Process, supply Voltage and Temperature (PVT) and aging-induced variations. It can be used during product lifetime, as a predictive delay fault detection technique, either to avoid unreliable operation, or to guarantee correct functionality with lower power consumption. The usefulness of the proposed technique is demonstrated with part of the data processor of a complex design for a medical imaging system used in PET-based mammography, configured in a Virtex-4 FPGA device (xc4vfx60-11ff1152).