João Paulo Teixeira

Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors

This paper presents a new approach on aging sensors for synchronous digital circuits. An adaptive error-prediction flip-flop architecture with built-in aging sensor is proposed, performing on-line monitoring of long-term performance degradation of CMOS digital systems. The main advantage is that the sensors performance degradation works in favor of the predictive error detection. The sensor is out of the signal path. Performance error prediction is implemented by the detection of late transitions at flip-flop data input, caused by aging (namely, due to NBTI), or to physical defects activated by long lifetime operation. Such errors must not occur in safety-critical systems (automotive, health, space). A sensor insertion algorithm is also proposed, to selectively insert them in key locations in the design. Sensors can be always active or at pre-defined states. Simulation results are presented for a balanced pipeline multiplier in 65 nm CMOS technology, using Berkeley Predictive Technology Models (PTM). It is shown that the impact of aging degradation and/or PVT (Process, power supply Voltage and Temperature) variations on the sensor enhance error prediction.

Low-sensitivity to process variations aging sensor for automotive safety-critical applications

In this paper, circuit failure prediction by timing degradation is used to monitor semiconductor aging, which is a safety-critical problem in the automotive market. Reliability and variability issues are worsening with device scaling down. For safe operation, we propose on-chip, on-line aging monitoring. A novel aging sensor (to be selectively inserted in key locations in the design and to be activated from time to time) is proposed. The aging sensor is a programmable delay sensor, allowing decision-making for several degrees of severity in the aging process. It detects abnormal delays, regardless of their origin. Hence, it can uncover “normal” aging (namely, due to NBTI) and delay faults due to physical defects activated by long circuit operation. The proposed aging sensor has been optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Moreover, the area overhead of the new architecture is significantly less than the one of other aging sensors presented in the literature. Simulation results with a 65 nm sensor design are presented, ascertaining its usefulness and its low sensitivity, in particular to process variations.

Predictive error detection by on-line aging monitoring

The purpose of this paper is to present a predictive error detection methodology, based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI), or to physical defects activated by long lifetime operation, which may occur in safety-critical systems (automotive, health, space). Error is prevented by detecting critical paths abnormal (but not fatal) propagation delays. A monitoring procedure and a programmable aging sensor are proposed. The sensor is selectively inserted in key locations in the design and can be activated either on users requirement, or at pre-defined situations (e.g., at power-up). The sensor is optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Sensor limitations are analysed. A new sensor architecture and a sensor insertion algorithm are proposed. Simulation results are presented with a ST 65 nm sensor design.

Programmable aging sensor for automotive safety-critical applications

Electronic systems for safety-critical automotive applications must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasing. One of the key reliability issues is long-term performance degradation due to aging. For safe operation, aging monitoring should be performed on chip, namely using built-in aging sensors (activated from time to time). The purpose of this paper is to present a novel programmable nanometer aging sensor. The proposed aging sensor allows several levels of circuit failure prediction and exhibits low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Simulation results with a 65 nm sensor design are presented, that ascertain the usefulness of the proposed solution.

Built-in aging monitoring for safety-critical applications

Complex electronic systems for safety or mission-critical applications (automotive, space) must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasing. One of the key reliability issues is to monitor long-term performance degradation due to aging in such harsh environments. For safe operation, or for preventive maintenance, it is desirable that such monitoring may be performed on chip. On-line built-in aging sensors (activated from time to time) can be an adequate solution for this problem. The purpose of this paper is to present a novel methodology for electronic systems aging monitoring, and to introduce a new architecture for an aging sensor. Aging monitoring is carried out by observing the degrading timing response of the digital system. The proposed solution takes into account power supply voltage and temperature variations and allows several levels of failure prediction. Simulation results are presented, that ascertain the usefulness of the proposed methodology.

Design and test issues of a FPGA based data acquisition system for medical imaging using PEM

The main aspects of the design and test (D&T) of a reconfigurable architecture for the data acquisition electronics (DAE) system of the clear-PEM detector are presented in this paper. The application focuses medical imaging using a compact PEM (positron emission mammography) detector with 12288 channels, targeting high sensitivity and spatial resolution. The DAE system processes data that comes from a front-end (FE) electronics that identifies the relevant data and transfers it to a PC for image processing. The design is supported in a novel D&T methodology, in which hierarchy, modularity and parallelism are extensively exploited to improve design and testability features. Parameterization has also been used to improve design flexibility. Nominal frequency is 100 MHz. The DAE must respond to a data acquisition rate of 1 million relevant events (coincidences) per second, under a total single photon background rate in the detector of 10 MHz. Trigger and data acquisition logic is implemented in eight 4-million, one 2-million and one 1-million gate FPGAs (Xilinx Virtex II). Functional built-in self test (BIST) and debug features are incorporated in the design to allow on-board FPGA testing and self-testing during product lifetime

Performance simulation studies of the clear-PEM DAQ/trigger system

The clear-PEM detector is a positron emission mammography scanner based on high-granularity avalanche photodiodes readout with 12 288 channels. The front-end sub-system is instrumented with low-noise 192:2 channel amplifier-multiplexer ASICs and free-running sampling ADCs. The off-detector trigger, implemented in a FPGA based architecture, computes the pulses amplitude and timing required for coincidence validation from the front-end data streams. A high-level C++ simulation tool was developed for data acquisition performance analysis and validated at bit level against FPGA VHDL testbenches. In this work, simulation studies concerning the performance of the on-line/off-line energy and time extraction algorithms and the foreseen detector energy and time resolution are presented. Time calibration, trigger efficiency and ghosting are also discussed

Signal Integrity Enhancement in Digital Circuits

This article proposes a new methodology for enhancing SoC signal integrity without degrading performance in the presence of power-ground voltage transients. The underlying principle is the dynamic adaptation of the clock duty cycle to propagation delay variation along disturbed logic paths. This methodology makes digital circuits more robust to power line fluctuations while maintaining the at-speed clock rate.

Dynamic fault test and diagnosis in digital systems using multiple clock schemes and multi-VDD test

Performance test is a powerful technique to identify difficult to detect defects. Recently, the authors have shown that multi-VDD test schemes may be used in a BIST environment to simulate multi-clock test. Using circuit and logic-level fault simulation it has been demonstrated that the effect of lowering VDD on the propagation delay time, while keeping invariant the observation pace at speed test, is similar to the effect of decreasing the clock period tCLK while keeping nominal VDD. In this paper, a simple analytical model to represent the dependence of propagation delay time variations of logic elements, Δpd on depleted VDD (i.e., on ΔVDD) is introduced. The model allows to back-annotate this dependence to logic-level fault simulation. As clock period decreases (or VDD decreases) failing vectors inducing errors are identified. Performance histograms, describing the dependence of the number of failing vectors on higher clock speed (or lower VDD) are used for delay fault detection and defect diagnosis. Basic infrastructures, ISCAS benchmarks and a combinational block of an industrial fleet management system, XTRAN, is used to demonstrate the results.

Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip

This paper addresses the modeling and simulation of power supply voltage transients (Δ VDD) in digital SoC (Systems on a Chip), namely their impact on SoC core’s performance. The goal is to verify, in a cost-effective way, core’s fault tolerance to this disturbance, aiming at EMI/EMC standard compliance. The two key parameters are the time slack and the defect size. A top-down approach is used to introduce an innovative fault injection and simulation technique. In fact, fault simulation is carried out either by using faulty delays (defect size as a function of Δ VDD magnitude) in the CUT (Core Under Test) and nominal time excitation rate, or by using a fault-free CUT description and faster test application times (speed-up proportional to Δ VDD magnitude). A bottom-up approach, using electrical simulation, is extensively used to demonstrate the adequacy of exploiting this duality between time excitation and delay response, for combinational CUT. We refer this duality as the “accordion” effect. For sequential circuits, and for pipeline circuits, it is shown that the tolerance to Δ VDD disturbances is significantly lower than the one observed in combinational CUT, due to de-synchronization effects in storage elements. This effect depends on the clock distribution network and is a consequence of differently delayed responses of the CUT and of the clock network. Results are demonstrated using basic infrastructures and ISCAS benchmark circuits.