Carlos Marquez

Electrical characterization and conductivity optimization of laser reduced graphene oxide on insulator using point-contact methods

The present work is focused on the electrical characterization of laser-assisted reduced graphene oxide by point-contact techniques. The aim is twofold: firstly, the careful investigation of in-line two and four point-contact techniques applied to macroscopic samples of reduced graphene oxide. The combination of both methods has shed light on the role of the point-contact when extracting the intrinsic resistivity of the material. Secondly, once the measurement protocol is well understood, it is applied to improve the conductivity of the samples by the adjustment of the initial colloid concentration and the photothermal power intensity used for the reduction. The final optimized samples present promising conductivity, comparable to that of large graphene sheets obtained by chemical vapor deposition methods.

Determination of ad hoc deposited charge on bare SOI wafers

This work develops an analytical model which correlates the changes of the threshold voltages in Pseudo-MOSFET structures with the charge intentionally placed on the surface of the native oxide. The model has been validated through experimental I-V characteristics obtained when the surface is physically altered with an APTES solution. The measurements were performed in 15 MESA isolated SOI cells. These results open the path for the potential use of the bare SOI wafers as a platform for charge-based sensing applications.

On the effective mobility extraction by point-contact techniques on silicon-on-insulator substrates

In this work, we introduce the mobility vs. effective electric field representation for bare silicon-on-insulator substrates. The key factors determining the effective field in the silicon film are identified and modeled. This representation sheds light on the origins of the carrier mobility differences observed in passivated and non-passivated wafers. At low effective electric field, the roles of the Coulomb scattering, determined by the top-interface, and the impact of the silicon film thickness are clearly disclosed. Two and four point-contact characterization techniques are compared; caution is called when the two point Pseudo-MOSFET configuration is used without calibration of the current form factor, since it may lead to an underestimation of the mobility values. Nevertheless, when the effective field and current form factors are evaluated accurately, we report that the carrier mobility of the silicon film at high effective electric field, with passivated surface or not, obeys the Universal Mobility...

In Situ Characterization of Bias Instability in Bare SOI Wafers by Pseudo-MOSFET Technique

Bias instability is a reliability issue affecting the electrical characteristics of a MOS transistor when the gate is stressed with relatively high voltage. For the first time, we characterize the instability of bare SOI wafers using the pseudo-MOSFET technique. The effect of positive and negative stress pulses on the properties of both hole and electron channels is systematically investigated using measure-stress-measure and on-the-fly methods. The origin of the instability, the dependence of the degradation with time, and the recovery after the stress are discussed.

Fabrication and validation of A2RAM memory cells on SOI and bulk substrates - Withdrawn

Withdrawn.

Insights on the Body Charging and Noise Generation by Impact Ionization in Fully Depleted SOI MOSFETs

Thin and ultrathin body-contacted Silicon-on-Insulator MOS-transistors have been used for the direct experimental measurement of the stationary body potential and impact ionization current generated at moderate and high electric field regimes. The large influence of the channel length on the evolution of the body potential as well as the severe loss of electrostatic control of the body by the gate terminal due to the hole injection have been successfully monitored through the body-contact. In our short devices, the impact ionization current tends to saturate as the gate bias increases for high values of the drain bias, whereas the impact ionization ratio has been found to be larger at low inversion charge. At moderate impact ionization regime, an update set of experimentally extracted ionization coefficients have been proposed revealing significant differences with the ones used in bulk technologies. Finally, low-frequency noise characterization has shown the impact ionization contribution to the fluctuation of the drain current. The power spectral density of the noise at the body-contact of the transistor has revealed the signature of the parasitic bipolar triggering at high impact ionization regime.

Electrical characterization of Random Telegraph Noise in back-biased Ultrathin Silicon-On-Insulator MOSFETs

Random Telegraph Noise (RTN) has been studied in ultrathin SOI MOSFET by introducing a new protocol which aims to identify unequivocally the single-trap RTN signals in optimum bias conditions for its electrical characterization. The methodology combines a modified Weighted Time Lag Plot algorithm assisted with 1/f spectral scanning by gate bias. The procedure has been applied to study the influence of the back-gate bias on the RTN characteristics of the SOI devices with coupled front and back interfaces, revealing unusual characteristics compatible with the trap escaping to the gate metal contact.

A2RAM: Low-power 1T-DRAM memory cells compatible with planar and 3D SOI substrates

A novel concept of multi-body 1T-DRAM cell fully compatible with both planar Silicon-On- Insulator substrates and 3D architectures is presented. Its scalability is ensured thanks to the dedicated body partitioning for hole storage and electron current sensing, suppressing the super-coupling effect and allowing the coexistence of electron and hole layers in very thin silicon films. Numerical simulations of the electrostatics and dynamic operation show attractive performance in terms of state discrimination and retention time. These theoretical results on planar devices have been experimentally validated on structures fabricated at CEA-LETI. Finally, we will demonstrate that this body-partitioning concept is extrapolated to 3D tri-gate structures showing high scalability, low-power consumption, long retention time, nondestructive reading, and wide memory window.

Tri-Dimensional A2-RAM Cell: Entering the Third Dimension

Chapter we present an overview of a capacitor-less DRAM cell based on a 3D multibody transistor with high scalability, low-power consumption, long retention time, non-destructive reading, and wide memory window. High performance is demonstrated on a 20 nm channel length device, including ‘1’ to ‘0’ current ratio larger than 103 (with negligible ‘0’ current level), very low voltage bias operation and retention time longer than 20 ms at 85 °C in worst cases. Compared to previous equivalent 3D memory cells reported so far, the proposed cell shows longer retention time even though the gate length is shrunk by a factor of two. The voltages used to write and read the information are far smaller than the previously reported ones in comparable structures. We have confirmed by TCAD simulation that the improvements are attributed to an innovative operation concept: a dedicated body partitioning. This device exploits the working principle of the A2RAM memory cell recently introduced by researchers at the University of Granada and Grenoble INP. The principles of operation and key mechanisms for programming are described. The new concept of 3D (FinFET, trigate or nanowire) DRAM cell proposed features a N/P body partitioning which enables the physical separation of hole storage and sensing electron current. The hole concentration in a surrounding P-crust, controls the partial or full depletion of a N-core which short-circuits drain and source of the device. The status of the N-bridge (depleted or un-depleted) determines the two memory logic states. The cell is compatible with ultimate scaling and shows attractive performance (long retention, wide memory window, simple programming, nondestructive reading, and very low-power operation) for embedded systems.

Direct point-contact characterization of Bias instability on bare SOI wafers

Bias Instability is a reliability issue affecting the threshold voltage of a MOS transistor when the gate is stressed with relatively high voltage. For the first time, we characterize the instability of bare SOI wafers using a Pseudo-MOSFET configuration. The effect of positive and negative stress pulses on the properties of both hole and electron channels is systematically investigated. The origins of the instability, the dependence of the degradation with time, and the recovery after the stress have been discussed.dependence