Noel Rodriguez

A-RAM Memory Cell: Concept and Operation

Capacitorless single-transistor (1T) DRAM cells are envisioned for replacing the conventional DRAMs where the storage capacitor can hardly be further miniaturized. We propose a totally different 1T-DRAM cell, named A-RAM, which is compatible with SOI CMOS deep scaling. Its novelty comes from the partitioning of the transistor body into two distinct ultrathin regions separated by a thin dielectric. The holes are physically confined in the upper semibody and govern the electron current flowing into the lower semibody. The systematic simulations show that the A-RAM is attractive for low-power and embedded memory applications since it exhibits enhanced state definition, retention, scalability, and simple waveforms for word and bit lines.

Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible With Bulk and SOI Substrates

A new concept of multibody single-transistor dynamic-random-access-memory cell fully compatible with both standard bulk and silicon-on-insulator substrates is presented. Its novelty comes from the juxtaposition of two silicon films with opposed doping polarities (i.e., a p-n junction), which define a body partitioning for hole storage and current sense. The charge accumulated in the top body controls the current flowing through the bottom body. The scalability is ensured due to the suppression of the supercoupling effect, thus allowing the coexistence of electrons and holes in very thin transistors. Numerical simulations of electrostatics and dynamic operation show how the transient response of this device can be used for dynamic-memory applications, achieving attractive performance in terms of state discrimination and retention time in very scaled devices.

Influence of acoustic phonon confinement on electron mobility in ultrathin silicon on insulator layers

We show the importance of acoustic phonon confinement in ultrathin silicon-on-insulator inversion layers by comparing electron mobility calculated by the Monte Carlo method assuming a bulk acoustic phonon model (the usual procedure) with that obtained by using a confined acoustic phonon model developed in this work. Both freestanding and rigid boundary conditions are taken into account for the evaluation of the confined phonon dispersion in a three-layer structure. Mobility reductions of 30% are observed for silicon thicknesses of around 5–10nm when the confined acoustic phonon model is used.

Revisited Pseudo-MOSFET Models for the Characterization of Ultrathin SOI Wafers

The pseudo-MOS transistor (Psi-MOSFET characteristics) is a simple and successful technique for the monitoring of silicon-on-insulator (SOI) wafer quality. To characterize modern ultrathin films, a reconsideration and review of Psi-MOSFET physics and models is required. Selected numerical simulations are presented, which shed light on the intriguing features governing Psi-MOSFET characteristics. Updated models accounting for the density of interface states and channel-to-surface coupling effects in ultrathin SOI wafers with passivated and nonpassivated surfaces are derived. These analytical models show excellent agreement with measurement and simulation data.

Why the Universal Mobility Is Not

Examples taken from ultrathin silicon-on-insulator (SOI) transistors tend to contradict the universality of mobility-field dependence. We revisit the meaning of the effective field concept and its implications on the universal mobility curve (UMC). Poisson-Schroedinger simulations point out the inappropriateness of the standard definitions of effective field when dealing with SOI or double-gate devices. Different carrier distributions can lead to the same value of the effective field breaking the foundation of the universality. The presence of two different gate stacks, the coexistence and coupling of two channels, and the spreading of carriers in the body are interesting nonlocal effects that are not accounted for by the UMC. Selected practical results showing the UMC failure in SOI metal-oxide-semiconductor field-effect transistors are presented. The actual behavior of the effective mobility is illustrated, shedding light on the limitations of the universal mobility/effective field representation.

Simulation of hole mobility in two-dimensional systems

We develop a fully self-consistent solver for the six-band k ⋅ p Schrodinger and Poisson equations to compute the valence-band structure of Si and Ge devices with arbitrary substrate orientation and uniaxial or biaxial strain. This allows us to compute the potential, charge distribution and subband energy dispersion relation for hole inversion layers in different devices and, using a simplex Monte Carlo simulator, to evaluate the low-field mobility. New procedures have been developed to calculate the scattering rates. The results obtained in the case of a (0 0 1) Si MOSFET device are compared with experimental mobility curves and a very good agreement is found. Then, hole mobility curves for different structures and crystallographic orientations both with strained and unstrained materials are evaluated.

A-RAM: Novel capacitor-less DRAM memory

A totally different capacitor-less, single-transistor memory cell (1T-DRAM) is proposed and documented. Its novelty comes from the body partitioning in two distinct regions, where electrons and holes are respectively confined. As compared to earlier 1T-DRAMs, the coexistence and coupling of electrons and holes is maintained even in ultrathin fully depleted MOSFETs. Selected simulations demonstrate attractive performance and great potential for embedded memory applications.

Experimental Demonstration of Capacitorless A2RAM Cells on Silicon-on-Insulator

We report the fabrication and characterization of A2RAM capacitorless memory cell on silicon-on-insulator (SOI). Holes and electrons are separated in two superposed p- and n-channel regions. The retrograde p-n doping in a 36-nm-thick body has been successfully tailored by epitaxial regrowth, without any alteration of the CMOS/SOI process. We document the detailed device operation and its attractive performance in terms of current margin, retention time, and variability.

An Analytical

A new analytical model is presented for the inversion charge of surrounding-gate transistors (SGTs). Quantum effects are taken into account by means of a modified capacitance model that includes the inversion charge centroid and a correction to the threshold voltage. A drain current model for the SGT that includes velocity saturation, short channel, and velocity overshoot effects is also developed. The model accurately reproduces both simulated and experimental results for different silicon core radii and gate voltages.

I

An empirical expression is developed for the inversion layer centroid and the polysilicon-gate depletion region thickness for bulk MOSFETs with different crystallographic orientations. In particular, results for the most commonly used wafer orientations, i.e., (100), (110), and (111), are given. These expressions are used to accurately model the inversion charge (Qinv) and the gate-to-channel capacitance (Cgc) of MOSFETs with gate oxides of nanometric thickness (tox < 1 nm) and different surface orientations. The Poisson and Schrodinger equations are self-consistently solved for different values of silicon and polysilicon doping concentrations in these devices. The results show important reductions of both Qinv and Cgc because of the polysilicon depletion effect and the displacement of the inversion charge centroid from the interface to the silicon bulk as a consequence of quantum effects. These effects are very noticeable for gate-oxide thicknesses of around 1 nm and must be taken into account in the development of accurate MOSFET models. The authors show that this task can be performed by means of a corrected gate-oxide thickness, which includes both the effect of the inversion layer centroid ZI and the polydepletion region thickness Z D. To do this, the authors have developed an accurate model for ZI as a function of the inversion charge concentration, the depletion charge concentration, and the silicon doping concentration for the (100), (110), and (111) wafer orientations. The in-plane channel directions have been swept for each wafer orientation in order to study the validity of the model in depth. Similarly, an expression for ZD as a function, of the polydoping concentration is provided. The gate-to-channel capacitance is also carefully and extensively analyzed. An analytical model for Cgc is provided and tested for different values of oxide thickness, polysilicon doping, substrate doping, and gate voltage