Carlos Paiz

vMAGIC—Automatic Code Generation for VHDL

Automatic code generation is a standard method in software engineering, improving the code reliability as well as reducing the overall development time. In hardware engineering, automatic code generation is utilized within a number of development tools, the integrated code generation functionality, however, is not exposed to developers wishing to implement their own generators. In this paper, VHDL Manipulation and Generation Interface (vMAGIC), a Java library to read, manipulate, and write VHDL code is presented. The basic functionality as well as the designflow is described, stressing the advantages when designing with vMAGIC. Two real-world examples demonstrate the power of code generation in hardware engineering.

The Utilization of Reconfigurable Hardware to Implement Digital Controllers: a Review

This paper reviews the impact of Reconfigurable Hardware (RH) on the design of digital controllers. It starts by showing the application areas in which this technology has more influence. The reasons of the technology migration are then analyzed, pointing specific examples from the literature. Finally, run-time reconfiguration (RTR) of Field Programmable Gate Arrays (FPGAs) is revised and its utilization for designing FPGA-based controllers is presented. The research trends are shown, giving an insight on the potential benefits of using this technology.

FPGA-in-the-loop-simulations for dynamically reconfigurable applications

This contribution presents a hardware-in-the-loop (HiL) design environment for FPGA-based systems. The presented tool-flow supports a two-stage verification process: A cycle-accurate HiL simulation using well-known simulation tools such as MATLAB/Simulink or Modelsim, and a real-time test using the target environment of the Design Under Test (DUT). The first stage allows an early verification of the DUT using a simulated environment, while the focus of the second stage is on monitoring internal states and I/Os of the DUT in operation, and on adjusting design parameters. All hardware and software interfaces required for both stages are generated individually and automatically by our tool-flow. The demo shows the benefits of using the presented HiL framework for applications targeting dynamic hardware reconfiguration. As an example, a two-controller system for an inverted pendulum is presented, where either a real system or an FPGA-based model combined with an augmented reality 3D animation can be used.

A design framework for FPGA-based dynamically reconfigurable digital controllers

During the past years, it has been shown that dynamic reconfiguration of FPGAs can be used to enhance the resource efficiency and flexibility of digital controllers. The authors have developed a system architecture, which allows the reconfiguration of FPGA-implemented controllers during runtime. Depending on the operating regions of the controlled plant different controllers can be dynamically loaded into the system. In this paper we present a design flow that enables an automated generation of such partial controllers. Furthermore, a high-level design entry allows a comfortable simulation of the controllers with sophisticated tools such as Matlab Simulink.

Digital signal processing for an adaptive phase-locked loop controller

Many piezoelectric systems are operated in resonance, requiring some sort of control. Especially weakly damped systems need a control algorithm to hold the system in resonance. There are many factors, which can change the systems resonant frequency during operation. The two most important factors are load effects and temperature effects. A common algorithm to drive a piezoelectric system in its eigenfrequency is the PLL (phase-locked-loop) controller - well known from communication technologies - including some adaptive variantions of the PLL. Beside a brief introduction into the APLL (adaptive PLL, this paper concentrates on one of the main components of the (A)PLL, the phase detector. It investigates and compares different types of phase detectors with a focus on the implantation on a digital control system.

Run-time reconfiguration of FPGA-based drive controllers

In this contribution a field programmable gate array (FPGA) is used as target architecture to implement drive controllers. A novel concept for generic run-time switching between FPGA-based drive controllers is presented. The controller switching is done by using partial run-time hardware reconfiguration, which allows the implementation of various controllers without having to realize them all on the FPGA concurrently. It is shown that time-sharing of the FPGA resources can provide a resource-efficient implementation. A system architecture, which enables the realization of this scheme, is presented. A hard switching between controllers is implemented, for which the initial internal states of the controller to-be-loaded are computed. Experimental results show that the proposed scheme works satisfactory, opening new possibilities to the implementation of such adaptive control schemes.

Hardware-in-the-Loop Simulations for FPGA-based Digital Control Design

A framework to perform hardware-in-the-loop (HIL) simulations in the designflow of digital controllers, based on Field Programmable Gate Array (FPGA) technology, is presented. The framework allows the interaction of digital controllers, implemented on our rapid prototyping system RAPTOR2000 with a Matlab/Simulink simulation running on a host computer. The underlying hardware and software designs supporting the interaction of the digital control and the simulation are presented. The designflow of FPGA-based digital controllers when using HIL is described and examples are given. Results from HIL simulations are presented, showing that the acceleration of the simulation increases with the complexity of the design when the number of I/Os stays constant. Furthermore, using the proposed HIL framework the clock accurate verification of the design can be achieved within the design phase.

Dynamically Reconfigurable Hardware for Autonomous Mini-Robots

Reconfigurable hardware (e.g., field programmable gate arrays - FPGAs) has been successfully used as processing units in various mini-robotic applications. In this work, we pursue to improve the utilization of reconfigurable hardware by introducing dynamic reconfiguration. A hardware-software architecture is presented, which enables the realization of dynamic reconfiguration for usage on autonomous mini-robots. Two application examples are presented. The first application is dealing with principles of reconfigurable digital controllers, the second is image processing in the context of robot vision. Platforms for the implementation of the principles are the mini-robot Khepera as well as a novel mini-robot providing dynamic reconfiguration and a chassis fabricated in MID technology for integrating mechanical and electrical components

FPGA-based realization of self-optimizing drive-controllers

An FPGA (Field Programmable Gate Array) implementation and suitable power electronics can lead to a fast torque response in motion drive applications. However, when the controller parameters or its structure have to be adapted to internal and external varying conditions, e.g., when a self-optimizing control system is pursued, a static implementation might not lead to the best utilization of reconfigurable resources. This contribution outlines the implementation of a self-optimizing system composed of several possible hardware and software realizations of controllers for a permanent magnet servo motor. How well a specific controller realization is suited to the current situation is evaluated based on control quality and realization effort (i.e., CPU time, reconfigurable area). A System-on-Chip architecture is presented, which enables an on-line exchange of FPGA- and CPU-based realizations of controllers to optimize resource utilization and control quality. It is shown that by using dynamic hardware reconfiguration, such self-optimizing controller can be implemented based on FPGA technology. Furthermore, the design-flow including self-developed tools is outlined. Experimental results show that the proposed scheme works satisfactory.

Dynamically reconfigurable hardware for digital controllers in mechatronic systems

Reconfigurable hardware, and particularly field programmable gates arrays (FPGAs) allow the acceleration of digital control algorithm for mechatronic systems by exploiting their intrinsic parallelism. FPGAs also allow an efficient use of resources and flexible designs by using partial and dynamic reconfiguration. However, fully utilization of those benefits is often prevented by the necessary expertise to use such technology. In this paper a design flow for digital control algorithms using FPGAs is presented, which allows engineers without specialized knowledge on reconfigurable hardware design to use FPGAs as an implementation platform. We introduce a system architecture that enables the use of partially dynamic reconfiguration of FPGAs as part of our design flow and show an implementation example using an inverted pendulum system.