Carmine Cappetta

Multiplier-Less Stream Processor for 2D Filtering in Visual Search Applications

A new 2D convolution-based filter is presented, which is specifically designed to improve visual search applications. It exploits a new radix-3 partitioning method of integer numbers, derived from the weight partition theory, which allows substituting multipliers with simplified floating point (FP) adders, working on 32-b FP filter coefficients. The memory organization allows elaborating the incoming data in raster scan order, as those directly provided by an acquisition source, without frame buffers and additional aligning circuitry. Compared with the existent literature, built around conventional arithmetic circuitry, the proposed design achieves state-of-the-art performances in the reduction of the mapped physical resources and elaboration velocity, achieving a critical path delay of about 4.5 ns both with a Xilinx Virtex-7 field-programmable gate array and CMOS 90-nm std_cells.

FPGA optimization of convolution-based 2D filtering processor for image processing

The Bachet weight decomposition method is used to design a new 2D convolution-based filter, specifically aimed to image processing. The filter substitutes multipliers with simplified floating point adders to emulate standard 32 bit floating point multipliers, by using a set of pre-computed coefficients. A careful organization of the memory, together with the optimized distribution of the related hard macros in the FPGA fabric, allow the elaboration of the data in raster scan order, as those directly provided by an acquisition source, without the need of frame buffers or additional aligning circuitry. The proposed design achieves a state-of-the-art critical path delay of 4.7 ns on a Xilinx Virtex 7 FPGA.

Design and FPGA implementation of a real-time processor for the HDR conversion of images and videos

In this paper a multiresolution architecture to expand the dynamic range of low dynamic range (LDR) images to 32-bit high dynamic range (HDR) counterpart is presented. The processor is capable to provide on-the-fly calculation of the edge-preserving bilateral filtering and luminance average, to images images up to full-HD images (1920×1080 pixels) using 25×9 filtering and up to 4K UHDTV images (3840×2160 pixels) using 25×5 filtering without frame buffers. To this end, a “hardware friendly” algorithm has been derived from the most effective methods presented in the literature. Additionally, the proposed design is capable of processing the input pixel in streaming order, as they come from input devices by avoiding frame buffers and eliminating external DRAM. The processor complexity can be configured with different area/speed ratios in order to meet the requirements of different FPGA platforms. Implemented on a high-end FPGA the processor achieves state-of-the art performances.

Weighted Partitioning for Fast Multiplierless Multiple-Constant Convolution Circuit

A new radix-3 partitioning method of natural numbers, derived by the weight partition theory, is employed to build a multiplierless circuit that is well suited for multimedia filtering applications. The partitioning method allows conveniently premultiplying 32-b floating-point filter coefficients with the smallest set of parts composing an unsigned integer input. In this way, similar to the distributed arithmetic, shifters and recoding circuitry, typical of other well-known multiplier circuits, are completely substituted with simplified floating-point adders. Compared to the existent literature, targeted to both field-programmable gate array and std_cell technology, the proposed solution achieves state-of-the-art performances in terms of elaboration velocity, achieving a critical path delay of about 2 ns both on a Xilinx Virtex 7 and with CMOS 90-nm std_cells.

Application specific image processor for the extension of the dynamic range of images with multiple resolutions

A new processor is proposed, capable to expand the dynamic range of input images in real-time. With respect to the existent literature, the processor presents the unique feature of elaborating images at different resolutions, up to 4K UHDTV, by deriving a specific algorithm from the most effective methods presented in the literature. Additionally, the proposed design is capable to elaborate the input pixel in streaming order, as they come from input devices by avoiding frame buffers and eliminating external DRAM. The processor complexity can be configured with different area/speed ratios in order to meet the requirements of different FPGA platforms. Implemented on a high-end FPGA the processor exhibits a latency of 32.4ms (31 fps), while a 4K frame requires 129ms (8 fps) to be processed.

Hardware accelerator using Gabor filters for image recognition applications

This paper presents the design of a new hardware accelerator, filtering the input data using Gabor functions and dedicated to image processing. The proposed design obtains a great reduction in terms of resources if compared to other state-of-the-art implementations. This is done exploiting the separability of Gabor filters along certain orientations and through a reorganization of the arithmetic units and the memory structures, achieved thanks to the absence of frame buffers to store the entire input image and partially processed data. All the above reported features allow the design to obtain real-time performances. The design has been targeted to a Xilinx Virtex 7 ASIC board and to CMOS 90nm std_cells, obtaining a minimum operating clock period of 5.8 ns for the FPGA implementation and of 2.9 ns for the std_cell one. The above reported results allow to process 83 and 168 1920×1080 pixels (Full-HD) frame-per-second, respectively.

An FPGA oprimization of a multiple resolution architecture for LDR to HDR image conversion

An architecture capable of performing the inverse Tone Mapping to convert a Low Dynamic Range image into a High Dynamic Range one is proposed. The proposed image processor is specifically designed for a Field Programmable Gate Array implementation. The design exploits the presence of specific blocks in the Field Programmable Logic board, dedicated to the implementation of memories, in order to develop an efficient implementation to process images having a resolution up to 4K UHDTV. The proposed implementation is developed avoiding frame buffers to obtain a design showing low power and a reduced area, in addition to a real-time processing of the image up to Full-HD frames. The proposed scheme achieves state-of-the-art performances and is a lot more flexible than previously developed single resolution architectures.

Hardware architecture for 2D Gaussian filtering of HD images on resource constrained platforms

A bi-dimensional filter for high accuracy image processing is implemented by using a novel partitioning method. The method is based on a number theory theorem, which permits to reduce the complexity of the operation to that of an adder chain and also the amount of the coefficients stored in memory, improving the memory organization. To show the advantage of such method, we implemented a Floating Point 32 (FP32) in hardware filtering applications and, in particular, for 2D FIR filters. Using Xilinx Virtex 7 Field Programmable Gate Array (FPGA) we obtain a critical path delay of 4.7ns which is comparable with the state-of-art.

Optimal design of a Gabor filter for medical imaging applications

The Gabor filter has gained an important agreement in multimedia processing and visual search applications for its good spatial frequency and position selectivity, notwithstanding its heavy computational load. For these reasons, Gabor filters find useful applications in the processing of medical images, aiming to enhance the original image and to overcome issues related to noise and artifacts. With the purpose to find the optimal design of a Gabor filter to be implemented in ASIC and FPGA platforms, in this work three architectures are presented, representing the best trade-offs for accuracy, area and power constraints. A comparative study among the proposed architectures in terms of allocation of the resources, power dissipation and timing performances is presented, which reveals useful for an informed choice depending on the particular application. The designs have been implemented on a FPGA-based ASIC prototyping system, which returns a maximum operating frequency of 172 MHz for the best case. Synthesis with 90nm CMOS standard cell returns a maximum frequency of 350 MHz. Therefore, the fastest architecture processes 83 and 168 Full-HD (1920×1080 pixels) frames-per-second, respectively for a FPGA and an ASIC implementation, which, to the best of our knowledge, is the current state-of-the-art.

Dynamic range enhancement for medical image processing

A new Application Specific Image Processor for the enhancement of the dynamic range of medical images is presented, capable to process images at different resolutions up to 4K. An algorithm has been derived, adapted and tailored for the specific hardware design, in order to adapt the complexity of the processor to required performances or to constraints of different field programmable platforms. The proposed design achieves such results by the reduction of frame buffer elimination that reduces the amount of memory for processing and allows the implementation of smart image sensors. The implemented design returns state-of-the-art performances for both FPGA and std_cell implementation.