Gian Domenico Licciardo

An Analytical Model of the Switching Behavior of 4H-SiC p

An analytical model of the switching behavior of SiC diodes is presented. The model gives an accurate description of the current and voltage transient for a wide range of reverse to forward current ratios and allows one to evaluate the spatial-temporal distributions of carriers density, current components and electric field along the base at a generic instant of the whole transient. Using this model, a large-signal circuit is derived that is useful for circuital analysis of diode under generic operation conditions. The accuracy of the model is verified by comparisons with numerical simulations and experimental results.

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An electronic circuit for making accurate open-circuit voltage decay measurements is presented. The circuit overcomes the main limitations that occur in the standard method when used for carrier lifetime characterization because it realizes the ldquoopen-circuit conditionsrdquo of the device under test with an impedance higher than 100 MOmega and reduces the noise that is inherent in the differential operation of the method.

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A new analytical model of 4H-SiC DMOSFETs that is useful to explore their thermal stability is presented. The model is capable to describe, with closed-form equations, the dc forward behavior of devices in a wide temperature range, including the effects of parasitic resistances and oxide interface traps. The model allows to analyze the on set of electrothermal stability of 4H-SiC DMOSFETs both in triode and in saturation region and to monitor the impact of the series resistance and traps on reliable operation of devices. The accuracy of the model has been verified by comparisons with numerical simulations that evidence the effect of trap densities in the range [0-1014 ] cm-2 · eV-1 for operating temperatures up to 500 K. Comparisons with experimental data of 1.2 and 1.7 kV commercial devices are used to validate the model.

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The presence of crossing points in the forward JD-VD curves of 4H-SiC pin diodes is analyzed by means of numerical and analytical models. The analysis allows one to justify the different temperature coefficients reported in the literature for SiC diodes and the interlacing behavior of their JD-VD curves. A simple formula for predicting the position of the crossing-point is proposed.

Diodes from Arbitrary Injection Conditions

In this letter, the first experimental results of a recently proposed technique for measuring the carrier lifetime profile are presented. The technique makes use of a four-terminal bipolar test structure to electrically define the epilayer volume where recombination occurs and employs the open circuit voltage decay method for lifetime parameters extraction. For the capability of the test structure to depurate measurements from the parasitic ohmic effects, the technique is able to measure the ambipolar and minority carrier lifetime along epilayer at high and low injection levels respectively. Comparisons of measurements with numerical simulations are reported to confirm the validity of the proposed technique.

An Analog Circuit for Accurate OCVD Measurements

In this paper, an architecture design of a hardware accelerator capable to expand the dynamic range of low dynamic range images to the 32-bit high dynamic range counterpart is presented. The processor implements on-the-fly calculation of the edge-preserving bilateral filtering and luminance average, to elaborate a full-HD (1920

Analytical Model of the Forward Operation of 4H-SiC Vertical DMOSFET in the Safe Operating Temperature Range

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On the Crossing-Point of 4H-SiC Power Diodes Characteristics

1080 pixels) image in 16.6 ms (60 frames/s) on field-programmable logic (FPL), by processing the incoming pixels in streaming order, without frame buffers. In this way, the design avoids the use of external DRAM and can be tightly coupled with acquiring devices, thus to enable the implementation of smart sensors. The processor complexity can be configured with different area/speed ratios to meet the requirements of different target platforms from FPLs to ASICs, obtaining, in both implementations, state-of-the-art performances.

Experimental measurements of majority and minority carrier lifetime profile in SI epilayers by the use of an improved OCVD method

A new analytical description of the trapped charge distribution at the semiconductor-insulator interface of 4H-SiC vertical-DMOSFET has been derived as a function of the surface potential into the channel. The model allows one to accurately calculate the electrical characteristics of the device in both subthreshold and above-threshold operations, namely, when the channel works from weak accumulation to strong inversion. The accuracy of the model has been verified by comparisons with numerical simulations and with experimental measurements of a 1.7-kV commercial device.

Stream Processor for Real-Time Inverse Tone Mapping of Full-HD Images

An original model of the potential barrier in the channel of bipolar static induction transistors (BSITs) is presented. The model allows us to evaluate the potential barrier height for an arbitrary gate topology and to accurately predict the minority and majority carrier densities at the middle of the channel for a generic gate bias. The validity of the model is verified by comparison with numerical simulations of BSIT structures reported by other authors and with original simulations carried out on silicon (Si) and silicon carbide (SiC) junction field-effect transistors.