Luigi Di Benedetto

Analytical Model of the Forward Operation of 4H-SiC Vertical DMOSFET in the Safe Operating Temperature Range

A new analytical model of 4H-SiC DMOSFETs that is useful to explore their thermal stability is presented. The model is capable to describe, with closed-form equations, the dc forward behavior of devices in a wide temperature range, including the effects of parasitic resistances and oxide interface traps. The model allows to analyze the on set of electrothermal stability of 4H-SiC DMOSFETs both in triode and in saturation region and to monitor the impact of the series resistance and traps on reliable operation of devices. The accuracy of the model has been verified by comparisons with numerical simulations that evidence the effect of trap densities in the range [0-1014 ] cm-2 · eV-1 for operating temperatures up to 500 K. Comparisons with experimental data of 1.2 and 1.7 kV commercial devices are used to validate the model.

On the Crossing-Point of 4H-SiC Power Diodes Characteristics

The presence of crossing points in the forward JD-VD curves of 4H-SiC pin diodes is analyzed by means of numerical and analytical models. The analysis allows one to justify the different temperature coefficients reported in the literature for SiC diodes and the interlacing behavior of their JD-VD curves. A simple formula for predicting the position of the crossing-point is proposed.

Modeling of the SiO 2 /SiC Interface-Trapped Charge as a Function of the Surface Potential in 4H-SiC Vertical-DMOSFET

A new analytical description of the trapped charge distribution at the semiconductor-insulator interface of 4H-SiC vertical-DMOSFET has been derived as a function of the surface potential into the channel. The model allows one to accurately calculate the electrical characteristics of the device in both subthreshold and above-threshold operations, namely, when the channel works from weak accumulation to strong inversion. The accuracy of the model has been verified by comparisons with numerical simulations and with experimental measurements of a 1.7-kV commercial device.

A Model of the

The first analytical model of the transfer characteristics of normally OFF JFETs devices is presented. The model exploits an original description of carrier distributions in the channel as function of gate and drain voltages, which are then used to determine the barrier height and ID - VGS curves for a generic channel geometry and bias condition of the device. The generality of the model is proved by comparisons with numerical simulations of the barrier height and ID - VGS curves of Si and 4H-SiC JFETs, designed using different aspect ratios and doping, and with the measured ID - VGS curves of existing devices.

I_{\bm D} {-} V_{{\bf GS}}

An original model of the potential barrier in the channel of bipolar static induction transistors (BSITs) is presented. The model allows us to evaluate the potential barrier height for an arbitrary gate topology and to accurately predict the minority and majority carrier densities at the middle of the channel for a generic gate bias. The validity of the model is verified by comparison with numerical simulations of BSIT structures reported by other authors and with original simulations carried out on silicon (Si) and silicon carbide (SiC) junction field-effect transistors.

Characteristics of Normally OFF 4H-SiC Bipolar JFETs

An analytical instrument to design 4H-SiC planar and trenched junction barrier Schottky (JBS) diodes is proposed. The tool is based on a novel full analytical description of the electric field distribution into channel region of the device under reverse bias conditions. The model favorably exploits compact and reversible expressions that take into account all physical and geometrical quantities of the device in order to calculate the electric field at the Schottky contact as well as the reverse diode current, up to the occurrence of the physical limits of the Schottky junction. In contrast to the existing literature, the generality of the model is achieved by the absence of empirical parameters, since all the expressions are analytically derived. Finally, the capability of the analytical model to design generic JBS structures (planar, trenched, or recessed p-type regions) is shown in a step-by-step design process, too. Comparisons with numerical simulations and experimental data evidenced the high validity of the model and showed that it can be used both for high-voltage power diodes and for high switching frequency devices.

A Quasi-One-Dimensional Model of the Potential Barrier and Carrier Density in the Channel of Si and 4H-SiC BSITs

An original design of 4H polytype of silicon carbide (4H-SiC) bipolar-mode field-effect transistors (BMFETs), which combines the on-state operation of silicon version with the off-state behavior of SiC-VJFETs (vertical junction field-effect transistor), is analyzed by numerical simulations. Using the physical parameters extracted from the previous experimental analysis, this paper shows the feasibility of 4H-SiC BMFETs to manage drain current densities as high as 500 A/cm 2 with a current gain of 50 and to sustain blocking voltage of 2.1 kV. Comparisons with the existing 4H-SiC power transistors, like bipolar junction transistors (BJTs), VJFETs, and double-diffusive metal-oxide-semiconductor FETs, show that, besides a thermal stability in the examined range 300-523 K, BMFET exhibits the low on-resistance of BJTs and can operate at the high frequencies of power FETs.

Analytical Model and Design of 4H-SiC Planar and Trenched JBS Diodes

For the first time, a full analytical model of the electric field in the gate oxide of 4H-polytype silicon carbide (4H-SiC) power double-implanted MOSFET devices is shown. It takes into account all the relevant physical and geometrical parameters of the device and avoids the use of any fitting parameters. To validate the results of the full-analytical model, comparisons with numerical simulations are reported for device structures having different values of the drift doping concentration and drift thickness as well as of the junction FET (JFET)-region width. Moreover, because the model equations are in closed form, they can be used to derive an adequate JFET-region geometry by fixing the maximum electric field in the oxide and the maximum blocking voltage for a given drift region.

Design and Performances of 4H-SiC Bipolar Mode Field Effect Transistor (BMFETs)

A new 2D convolution-based filter is presented, which is specifically designed to improve visual search applications. It exploits a new radix-3 partitioning method of integer numbers, derived from the weight partition theory, which allows substituting multipliers with simplified floating point (FP) adders, working on 32-b FP filter coefficients. The memory organization allows elaborating the incoming data in raster scan order, as those directly provided by an acquisition source, without frame buffers and additional aligning circuitry. Compared with the existent literature, built around conventional arithmetic circuitry, the proposed design achieves state-of-the-art performances in the reduction of the mapped physical resources and elaboration velocity, achieving a critical path delay of about 4.5 ns both with a Xilinx Virtex-7 field-programmable gate array and CMOS 90-nm std_cells.

A Model of Electric Field Distribution in Gate Oxide and JFET-Region of 4H-SiC DMOSFETs

A novel model which is capable of describing with significant accuracy the temporal-spatial distributions of the minority carriers in 4H-SiC p-i-n diodes is presented. The analytical behaviour of the current, voltage and carrier distributions is compared with numerical simulations and with experimental results.