Carole D. Graas

Electromigration reliability improvement of W-plug vias by titanium layering

The electromigration (Er) performance of layered Al-0.5%Cu and Al-1%Si-0.5%Cu metallization systems was investigated, including leads with refractory barrier and capping layers, and tungsten-filled via holes. While the W-plugs exhibited a lifetime shorter than the leads, a dramatic improvement in EM performance of the vias was achieved by incorporating a thin layer of titanium between the aluminum and its cap. Among the most likely explanations for this observation is that the aluminum is protected from physical damage during via etch by the continuous TiAl/sub 3/ layer which forms by reaction between the titanium and the aluminum. Current flow simulations show complex crowding effects at the bottom of the vias. The role of grain boundaries and the effects of dopants on early via failure modes are also discussed.<<ETX>>

Correlations between initial via resistance and reliability performance

Accelerated stressing and electromigration (EM) testing were conducted on W-plug via chains and Van der Pauw structures respectively. These populations were chosen to include a wide distribution of initial resistances R/sub 0/. The high-end of the R/sub 0/ distribution exhibited a higher early failure rate and a higher spread in EM time-to-fail distribution. Processes which produce tightly controlled time-zero via resistance distributions are more desirable for via reliability.

Reliability challenges for deep submicron interconnects

Abstract Deep submicron interconnects (leads, contacts and vias) are rapidly becoming one of the major reliability challenges as ULSI devices continue to be scaled. With 0.5um feature sizes now common, trying to balance reliability and performance requirements is increasing difficult as we move toward 0.5 Ma/cm2 and single 0.20–0.25um contacts and vias will be required to safely carry 1–2ma of current. This increases electromigration concerns, with vias generally now being the weakest link in a reliable ULSI multilevel-metal system.

Designing and Building Reliability Into VLSI Interconnect Systems

The optimization of electromigration (EM) and stress-induced voiding (SV) properties of advanced interconnects impacts many critical system design parameters. In particular, the choice of materials and manufacturing processes must be carefully planned during the early phases of product development. In layered metallizations, both the barrier and capping layers design can affect electromigration resistance and stress-relaxation behavior, while electrical performance often constitutes a trade-off. This is shown specifically in a study of titanium diffusion into Al-Cu from TiN barrier layers, and in initial stress-relaxation tests characterizing the effect of Ti addition in the capping layer. The development of advanced characterization techniques supports the trial-and-error experimental optimization process, but models predicting EM and SV reliability are needed and should include complex sets of microstructural and design parameters.

Barrier layer effects and the use of Ti:W capping layers on the electromigration performance of Al-Si(1%)-Cu(0.5%) alloy

Electromigration performance is investigated for Al-Si(1%)-Cu(0.5%) alloy on a CVD-W or Ti:W barrier layer, and the effectiveness of a Ti:W capping layer to suppress electromigration is explored. Compared to a Ti:W barrier layer, the surface roughness of the CVD-W barrier layer degrades electromigration performance, however, a capping layer of Ti:W sequentially sputtered on top of the aluminum-alloy will substantively improve the electromigration performance when either barrier layer system is used. The improvement is observed to increase with the thickness of the Ti:W capping layer. Investigations of the failure kinetics and material properties indicate the EM performance improvement is primarily due to changes in the Al-alloy micro-structure.