Robert H. Havemann

High-performance interconnects: an integration overview

The Information Revolution and enabling era of silicon ultralarge-scale integration (ULSI) have spawned an ever-increasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. The increasing influence of interconnect parasitics on crosstalk noise and R(L)C delay as well as electromigration and power dissipation concerns have stimulated the introduction of low-resistivity copper and low-permittivity (k) dielectrics to provide performance and reliability enhancement. Integration of these new materials into integrated circuit fabrication is a formidable task, requiring material, process, design, and packaging innovations. Additionally, entirely new technologies such as RF and optical interconnects may be required to address future global routing needs and sustain performance improvement.

Damascene integration of copper and ultra-low-k xerogel for high performance interconnects

Copper has been successfully integrated in ultra-low k xerogel in a damascene structure. Resistance was shown to decrease by 30% with lower capacitance, relative to an aluminum/oxide baseline. For an equivalent resistance, an aluminum/oxide architecture would have 29% higher capacitance than that demonstrated here. Copper in xerogel trenches shows great promise as the next generation metallization system.

An 0.8µm CMOS technology for high performance logic applications

This paper reports on the process architecture and results of an 0.8µm 5V CMOS logic technology. The process, which is a factor of two faster than current 1.2µm CMOS technology, features seven optically patterned levels with 0.8µm geometries: isolation, gates, contacts, vias, TiN local interconnect (LI), and two metal levels.

A planarized multilevel interconnect scheme with embedded low-dielectric-constant polymers for sub-quarter-micron applications

The new embedded polymer structure combines the advantages of SiO/sub 2/ and low dielectric constant of polymeric materials. The interconnect performance is improved through line-to-line capacitance reduction by utilizing polymer only between tightly spaced lines. Double-level-metal interconnect structures have been successfully fabricated using a variety of low-dielectric-constant insulators. The new multilevel interconnect scheme alleviates many of the integration and reliability problems associated with polymers, and can be easily adopted to standard production process.<<ETX>>

An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capability

The authors describe the first high-performance, high-density ECL SRAM (emitter-coupled-logic static random-access memory) compatible with battery backup techniques. The 256K device has a measured access time of 8 ns. Fabricated in a 0.8- mu m BiCMOS process, the chip uses 117- mu m/sup 2/, full-CMOS, six-transistor memory cells and measures 6.5*8.15 mm/sup 2/. The design methodology described here illustrates the extent to which bipolar devices can be integrated into the periphery of a CMOS memory array. This integration was achieved through the use of a novel sensing scheme which provided three stages of bipolar differential sensing, with the first stage of sensing taking place directly on the bit lines. >

Overview Of Process Integration Issues For Low K Dielectrics

The era of silicon Ultra-Large-Scale-Integration (ULSI) has spurred an everincreasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. Both interconnect resistance and capacitance play key roles in overall performance, but modeling simulations have highlighted the importance of reducing parasitic capacitance to manage crosstalk, power dissipation and RC delay. New dielectric materials with lower permittivity (k) are needed to meet this challenge. This paper summarizes the process integration and reliability issues associated with the use of novel low k materials in multilevel interconnects.

Highly porous interlayer dielectric for interconnect capacitance reduction

Hydrogen silsesquioxane (HSQ) is a low density material for intra-metal gapfill, that offers low permittivity for interconnect capacitance reduction. Films with k as low as /spl sim/2.2 preferentially form between tightly-spaced metal leads when cured at low temperature (<400/spl deg/C), and interlayer dielectric properties are stable from 1 MHz to 1 GHz. HSQ simplifies the process integration of low-k materials for high performance interconnect applications by using standard semiconductor spin-on production techniques. Use of porous HSQ as a gapfill dielectric dramatically reduces the capacitive coupling between metal leads, resulting in higher interconnect performance.

An 8 ns BiCMOS 1 Mb ECL SRAM with a configurable memory array size

A 1-Mb*1 BiCMOS ECL (emitter-coupled-logic) I/O SRAM (static random access memory) is fabricated using a 0.8- mu m BiCMOS process. This memory device utilizes a 76- mu m/sup 2/ full-CMOS six-transistor memory cell, a dual-MOS current-source BiCMOS bit line sensing scheme, a BiCMOS current-source voltage reference network, and a low-capacitance load block line decoding circuit to achieve 8-ns access time. The configurable memory array size architecture allows for memory sizes from 64 kb up to 1 Mb in 64 kb increments with no change in the peripheral circuits. The six-transistor cell layout is shown, and the memory block architecture is illustrated. The low dependence of power supply current on the operating frequency shows the impact of ECL circuits in the design. Characteristics of the SRAM are summarized.<<ETX>>

A novel 0.25 /spl mu/m via plug process using low temperature CVD Al/TiN

A novel aluminum plug process is described which offers over a 3/spl times/ reduction in via resistance as compared with current tungsten plug technology. The performance advantage of the new process is further enhanced by its compatibility with low thermal budget, low-k dielectric materials, allowing significant reduction in the overall interconnect RC time constant. Key features of the Al plug technology include an over-hang free MOCVD (metal organic CVD) TiN liner, a single step low temperature (260/spl deg/C) chemical vapor deposition (LTCVD) of aluminum (resistivity <3 /spl mu/ohm-cm) and copper doping from an overlying PVD Al-Cu film. Double-level metal interconnects with 0.3 /spl mu/m vias and integrated low-k dielectrics were successfully fabricated using the new CVD TiN/Al technology. The 0.3 /spl mu/m diameter CVD Al plugs yielded >3/spl times/ lower via resistance compared with W plugs (1.5 vs. 5.0 ohms) with no degradation in electromigration reliability.

Integrated barrier/plug fill schemes for high aspect ratio Gb DRAM contact metallization

Abstract New contact fill integration schemes were developed for high aspect ratio Gb DRAM contact metallization. Integration schemes for both tungsten-plug contacts and aluminum-plug contacts were studied. For tungsten-plug contacts, various types of titanium liners and titanium nitride barriers were investigated and evaluated. These included collimated PVD (physical vapor deposition) titanium, ion metal plasma (IMP) titanium, and CVD (chemical vapor deposition) titanium liners; plasma enhanced CVD (PECVD) titanium nitride and plasma enhanced MOCVD (ECVD) titanium nitride barriers. The electrical results of 0.3 μm, 5:1 aspect ratio (AR) contact structures processed with a TiCl4-based CVD titanium liner and plasma enhanced CVD titanium nitride barrier show the lowest and the most tightly distributed contact parametrics. This is attributed to the conformal nature of the CVD process. In addition, the high titanium-deposition temperature, which leads to a simultaneous titanium silicide formation during the CVD titanium deposition process, may also have attribution to the low contact resistance and diode leakage obtained. In the case of aluminum-plug contacts, two different types of titanium nitride barriers (ECVD titanium nitride vs. silane-treated MOCVD titanium nitride) were evaluated and both showed comparable contact parametrics.