Qi-Zhong Hong

Self-aligned Ti and Co silicides for high performance sub-0.18 μm CMOS technologies

Abstract An overview of the development of advanced Ti and Co self-aligned silicide (SALICIDE) processes for deep-sub micron high performance CMOS technologies at Texas Instruments is presented. SALICIDES are a key factor for scaling of high-performance CMOS devices. They are used to lower sheet resistance of gate and source/drain regions, contact resistance and source/drain series resistance, increasing device performance and lowering RC delays to allow faster operation. Their applicability to deep-sub-micron technologies is determined by the fundamental materials aspects controlling silicide phase formation and evolution, as well as process integration issues such as effect of subsequent processing steps on the silicide films or effects of silicide related process steps on transistor characteristics. The main scaling issues for conventional processes, high resistivity on narrow lines for Ti SALICIDE and high diode leakage on shallow junctions for Co SALICIDE, are addressed. Detailed kinetic studies of the high resistivity to low resistivity phase transformations (TiSi2 C49 to C54 and CoSi to CoSi2) and their dependence on linewidth and film thickness are presented. A nucleation density model is shown to account for the measured linewidth dependence and effect of pre-amorphization implants on the TiSi2 C49 to C54 transformation and explain, as a result, narrow line sheet resistance. This overview covers studies on rapid thermal processing (RTP) for Ti and for Co SALICIDE, pre-amorphization implants and Mo impurities which allowed the first demonstration of low resistivity Ti SALICIDE at 0.10 μm gate lengths, as well as applications to sub-0.18 μm CMOS technologies and integration issues.

Salicides: materials, scaling and manufacturability issues for future integrated circuits

In this paper we present an overview of the development of advanced salicide processes at Texas Instruments, addressing both Ti and Co salicides. Scaling issues, such as sheet resistance of deep sub-micron structures for Ti salicide and diode leakage on shallow junctions for Co salicide, are discussed, as well as processes developed to overcome these issues. The key material aspects controlling these variables are reviewed, such as Ti silicide phase formation and transformations and mechanisms of direct formation of C54 TiSi2, which control sheet resistance, and silicide–silicon interface characteristics for Co salicide, impacting diode leakage. Implementation and manufacturability aspects are also discussed. We present advanced Ti and Co salicide processes with manufacturing and high yield capability demonstrated for sub-0.25 μm CMOS technologies. Process modifications that extend the applicability of these salicides to 0.1 μm CMOS are also presented.

Advanced salicides for 0.10 μm CMOS: Co salicide processes with low diode leakage and Ti salicide processes with direct formation of low resistivity C54 TiSi2

Abstract The scaling of CMOS technologies to 0.10 μm and beyond imposes increasingly demanding constraints to self-aligned silicide (salicide) processes. For high performance devices, it is essential that salicide processes achieve low gate and source-drain sheet resistance as well as low silicide to source-drain diffusion contact resistance, and maintain low junction leakage. This becomes increasingly difficult as junction depths and linewidths are scaled. In this paper we present an overview of the development of advanced Ti and Co salicide processes, with implementations into a high performance 0.10 μm complementary metal-oxide-semiconductor (CMOS) technology. For Co salicide, the main scaling issue is diode leakage on shallow junctions. We show that the use of pre-amorphization implants or a pre-Co deposition sputter etch improves diode leakage distributions, but fails to eliminate high leakage outliers. Co deposition temperature and rapid thermal processing (RTP) variables were found to have a strong effect on diode leakage, with optimization of either one resulting in tight low leakage distributions on shallow junctions. For conventional Ti salicide processes, the main scaling issue is sheet resistance on narrow lines due to incomplete high resistivity C49 TiSi 2 to low resistivity C54 TiSi 2 transformation. We present X-ray diffraction (XRD) and high resolution transmission electron microscopy (HRTEM) studies that indicate that direct growth of C54 TiSi 2 bypassing the C49 phase is achieved at low temperatures on polycrystalline or amorphous Si with the addition of Mo impurities, eliminating the narrow line effect. The mechanism is demonstrated to be nucleation of MoSi 2 and an unidentified phase at the Ti/Si interface, followed by epitaxial growth of C54 TiSi 2 on these templates. Ti salicide processes with Mo impurities were evaluated, demonstrating an optimized one-step RTP process combining Mo and pre-amorphization implants that maintains low sheet resistance to 0.06 μm gate lengths. Successful implementations into a 0.10 μm flow were achieved both for optimized Co salicide or Ti salicide processes.

Scaled CMOS technologies with low sheet resistance at 0.06-μm gate lengths

A novel Ti self-aligned silicide (salicide) process using a combination of low dose molybdenum and preamorphization (PAI) implants and a single rapid-thermal-processing (RTP) step is presented, and shown to be the first Ti salicide process to achieve low sheet resistance at ultrashort 0.06-/spl mu/m gate lengths (mean=5.2 /spl Omega//sq, max=5.7 /spl Omega//sq at 0.07 /spl mu/m; mean=6.7 /spl Omega//sq, max=8.1 /spl Omega//sq at 0.06 /spl mu/m, TiSi/sub 2/ thickness on S/D=38 nm), in contrast with previous Ti salicide processes which failed below 0.10 /spl mu/m. The process was successfully implemented into a 1.5 V, 0.12-/spl mu/m CMOS technology achieving excellent drive currents (723 and 312 /spl mu/A//spl mu/m at I/sub OFF/=1 nA//spl mu/m for nMOS and pMOS, respectively).

A Novel Process for Fabricating Conformal and Stable TiN‐Based Barrier Films

A new process for preparing TiN-based barrier films is reported. The process consists of thermal decomposition of a metallorganic precursor, tetrakis(dimethylamino)-titanium, followed by postdeposition annealing in silane ambient. Thin films fabricated using this approach have much higher stability and lower resistivity than those prepared using thermal decomposition alone. The new barrier films are conformal and exhibit good barrier performance for Al metallization.

Texture‐induced asymmetric reactions in TiN/Al–Cu/TiN

Thermally induced reactions in TiN/Al–Cu/TiN have been investigated. It is observed that the amount of the reactions is different at the two interfaces between Al–Cu and TiN. While there is minimal reaction between Al–Cu and the TiN overlayer, the reaction between Al–Cu and the TiN underlayer increases the sheet resistance of Al–Cu by as much as 15%. It is further shown that the asymmetric reactions are most likely caused by the different degree of (111) texture of TiN grown on amorphous SiO2 and textured, polycrystalline Al–Cu.

Thermal stability of Al/barrier/TiSix multilayer structures

Abstract The thermal stability of Al–0.5% Cu/barrier/TiSi x multilayer structures is investigated. The barriers studied in this work are TiN films prepared by physical vapor deposition (PVD) and TiN-based barrier films prepared by metal–organic chemical vapor deposition (MOCVD) with post-deposition anneal in silane. Sheet resistance, secondary ion mass spectroscopy (SIMS), diode leakage current and high spatial resolution electron microscopy measurements show significantly better thermal stability for structures using the silane-treated MOCVD barrier. Structural and composition differences of the two types of barriers are examined.

Novel Diffusion Barrier with Ultra-Thin Silicon Nitride Cap Layer

A novel type of diffusion barrier, consisting of a conducting layer whose surface is enriched with silicon nitride, was developed. The new barrier was prepared by thermal decomposition of a metal-organic precursor, tetrakis(dimethylamino) titanium (TDMAT), followed by in-situ silane anneal and subsequent surface nitridation. It combines the conformality and conductivity advantages of the underlying diffusion barrier with the good barrier properties of silicon nitride. The new barrier films were characterized by sheet resistance measurement, secondary electron micrographs (SEM) and x-ray photoelectron spectroscopy (XPS). The thermal stability of Cu/capped barrier/Si multilayer structures was demonstrated.

Mechanisms of Thin Film Ti And Co Silicide Phase Formation on Deep-Sub-Micron Geometries and Their Implications and Applications To 0.18 °m CMOS and Beyond

We studied the kinetics of the high resistivity to low resistivity phase transformation for Ti and Co silicides on deep-sub-micron geometries. Fundamental differences between the growth characteristics for Co and Ti result in different scaling behavior. While the the TiSi 2 C54 phase grows by a random nucleation and growth process from the polymorphic TiSi2 C49 phase, CoSi 2 grows by a diffusion limited process from CoSi. A strong linewidth and C49 grain size dependence for the TiSi 2 C49 to C54 transformation can be related to low nucleation density. A Johnson-Mehl-Avrami analysis was performed for the TiSi 2 C49 to C54 transformation obtaining the distribution of Avrami exponents and transformation times for individual 0.26 μm lines, showing that all lines transformed with similar one-dimensional growth characteristics. We found a strong dependence of the half-transformation times on film thickness and linewidth. While activation energies depend strongly on film thickness, ranging from 4.2 to 5 eV for films 64 to 28 nm thick, they are insensitive to linewidth indicating a different nature for the effect of linewidth and thickness. We also found a reduction of agglomeration temperatures with decreasing linewidth or film thickness resulting on a narrower process window for deep-submicron devices. A small linewidth dependence was measured for CoSi to CoSi 2 transformation rates, with activation energies of 2 to 2.2 eV for 0.27 μm and wider lines. Both Co and Ti selfaligned silicide processes were implemented successfully into a 0.18 μm technology.