Carolyn R. Ellinger

Metal-oxide thin-film transistors patterned by printing

We demonstrate thin-film transistors with the fabrication advantages associated with printed electronics and the device performance associated with inorganic materials that are typically patterned via photolithography. In this process a polymeric material is printed to selectively inhibit the deposition of the electrically active material, which is globally applied via spatial atomic layer deposition. We identify water-soluble inhibitors that make attractive choices for printable ink formulations and explore the interactions of two examples of polymeric inhibitors with the process space. Using this knowledge we demonstrate zinc oxide thin film transistors, patterned entirely by inkjet-printed polyvinyl pyrrolidone.

Design Freedom in Multilayer Thin-Film Devices

In fabricating inorganic thin-film devices, the relative etch rates of materials in a given etch chemistry often limit the obtainable multilayer structures. Alternatively, in fabricating multilayer organic devices by solution processing, the ability to formulate the active organic materials in orthogonal solvent systems is limiting. The pattered-by-printing method uses the combination of selective area deposition (SAD) and atomic layer deposition (ALD) to form high-quality metal oxide thin-film devices. We print an inhibiting polymer ink that patterns the functional inorganic materials that are deposited via spatial ALD (SALD). The process is inherently orthogonal, as the polymer ink does not etch or swell the inorganic functional layers. Each functional layer is additively patterned as deposited, with device isolation and vias defined by the printed inhibitor. The combination of process orthogonality and additive patterning removes processing-related constraints on device design, and readily allows for any combination of bottom- and top-gate thin-film transistor architectures to be formed on the same substrate. The freedom of this approach is further demonstrated by both all-enhancement-mode circuits and enhancement-depletion-mode circuits. In addition, we present a new tool to tune circuit performance by local control of dielectric thickness.

Improving Yield and Performance in ZnO Thin-Film Transistors Made Using Selective Area Deposition

We describe improvements in both yield and performance for thin-film transistors (TFTs) fabricated by spatial atomic layer deposition (SALD). These improvements are shown to be critical in forming high-quality devices using selective area deposition (SAD) as the patterning method. Selective area deposition occurs when the precursors for the deposition are prevented from reacting with some areas of the substrate surface. Controlling individual layer quality and the interfaces between layers is essential for obtaining good-quality thin-film transistors and capacitors. The integrity of the gate insulator layer is particularly critical, and we describe a method for forming a multilayer dielectric using an oxygen plasma treatment between layers that improves crossover yield. We also describe a method to achieve improved mobility at the important interface between the semiconductor and the gate insulator by, conversely, avoiding oxygen plasma treatment. Integration of the best designs results in wide design flexibility, transistors with mobility above 15 cm(2)/(V s), and good yield of circuits.