Carsten Linnenbank

On the matching behavior of MOSFET small signal parameters

An array test structure for precise characterization of the matching behavior of MOSFETs is presented. Besides the standard mismatch parameter drain current I/sub D/, the high resolution measurement principle allows the characterization of the small signal parameters transconductance g/sub m/ and in particular differential output conductance g/sub DS/. Measured data are shown to demonstrate the performance of the method. Whereas for the normalized standard deviations of I/sub D/ and g/sub m/ the well known proportionality to (WL)/sup -1/2/ is obtained, the normalized standard deviation of g/sub DS/ clearly deviates from this width and length dependence. For this parameter, proportionality to W/sup -1/2/ is found.

A novel approach for precise characterization of long distance mismatch of CMOS-devices

A new test structure is presented for the characterization of long distance mismatch of CMOS devices. A single circuit is used to characterize both transistors and resistors. High resolution is achieved by applying a four-terminal method with regulated reference potential to compensate for parasitic resistance effects. Measured data are presented for different CMOS processes to demonstrate the performance of this approach. In particular, the long distance matching behavior is compared to that of neighboring devices and examples for linear and nonlinear distance dependencies are shown.

Mismatch of MOSFET small signal parameters under analog operation

The matching behavior of drain current I/sub D/ and small signal parameters transconductance g/sub m/ and differential output conductance g/sub DS/ of MOSFETs is investigated under typical analog operating conditions. Whereas for the normalized standard deviations of I/sub D/ and g/sub m/ the well known proportionality to (W/spl times/L/sub eff/)/sup -1/2/ is obtained, the normalized standard deviation of g/sub DS/ clearly deviates from this width and length dependence. For this parameter, a proportionality to W/sup -1/2/ is found.

Precise quantitative evaluation of the hot-carrier induced drain series resistance degradation in LATID-n-MOSFETs

Abstract A method is presented which allows to distinguish the drain series resistance increase from other mechanisms contributing to the drain current degradation of hot-carrier stressed n-MOSFETs. Devices with different channel lengths but equal damages are used. The different degradation mechanisms are characterized quantitatively and a model for the drain current degradation is presented. For short stress times, the drain current degradation is dominated by series resistance degradation. For long stress times, however, the contribution of the mechanisms attributed to an “equivalent channel length increase” prevails.

The 65nm tunneling field effect transistor (TFET) 0.68/spl mu/m/sup 2/ 6T memory cell and multi-V/sub th/ device

The tunneling field effect transistor (TFET) is fabricated using a 65nm standard CMOS process flow. The short-narrow TFET offers an on-current of 550/spl mu/A//spl mu/m which is comparable to the reference MOSFET device. Due to the integrated substrate/well contact the effective area of the TFET is smaller compared to the corresponding MOSFET. Thus, the size of a system-on-a-chip design is reduced by more than 5%. The quantum-mechanical TFET is able to extend the epoch of the CMOS technology by showing reduced short channel effects and smaller leakage currents. A multi-threshold TFET device is proposed which does not need additional implantation steps. A 0.68/spl mu/m/sup 2/ 6 transistor memory cell is fabricated using TFETs and MOSFETs showing the compatibility of MOSFET and TFET and a decrease of the memory array area of approximately 3%.