Ulrich Schaper

On the matching behavior of MOSFET small signal parameters

An array test structure for precise characterization of the matching behavior of MOSFETs is presented. Besides the standard mismatch parameter drain current I/sub D/, the high resolution measurement principle allows the characterization of the small signal parameters transconductance g/sub m/ and in particular differential output conductance g/sub DS/. Measured data are shown to demonstrate the performance of the method. Whereas for the normalized standard deviations of I/sub D/ and g/sub m/ the well known proportionality to (WL)/sup -1/2/ is obtained, the normalized standard deviation of g/sub DS/ clearly deviates from this width and length dependence. For this parameter, proportionality to W/sup -1/2/ is found.

A novel approach for precise characterization of long distance mismatch of CMOS-devices

A new test structure is presented for the characterization of long distance mismatch of CMOS devices. A single circuit is used to characterize both transistors and resistors. High resolution is achieved by applying a four-terminal method with regulated reference potential to compensate for parasitic resistance effects. Measured data are presented for different CMOS processes to demonstrate the performance of this approach. In particular, the long distance matching behavior is compared to that of neighboring devices and examples for linear and nonlinear distance dependencies are shown.

A new test circuit for the matching characterization of npn bipolar transistors

A new test macro with an active device array is presented for the mismatch characterization of npn bipolar transistors. The macro contains a CMOS circuit which serves for the selection of each bipolar device individually. For each bipolar device terminal a force/sense method is employed to assure the high voltage accuracy requested for bipolar transistors. The characterization of the array with transistors of different geometry gives a database on chip level for the statistical analysis. Matching parameters are given for collector current, current gain, and base-emitter voltage of a 0.5 /spl mu/m smart power technology. The results agree well with in-line measurements using single device pairs and are comparable to reported values in the literature for corresponding technologies.

Mismatch of MOSFET small signal parameters under analog operation

The matching behavior of drain current I/sub D/ and small signal parameters transconductance g/sub m/ and differential output conductance g/sub DS/ of MOSFETs is investigated under typical analog operating conditions. Whereas for the normalized standard deviations of I/sub D/ and g/sub m/ the well known proportionality to (W/spl times/L/sub eff/)/sup -1/2/ is obtained, the normalized standard deviation of g/sub DS/ clearly deviates from this width and length dependence. For this parameter, a proportionality to W/sup -1/2/ is found.

Matching Model for Planar Bulk Transistors With Halo Implantation

Threshold voltage matching of long-channel planar bulk transistors deteriorates strongly by halo implantations compared to the matching of nonhalo devices which follow a gate area dependence (Pelgroms model). A new compact matching model explains the observations and extends Pelgroms model to halo transistors using the Vt(L) behavior of the device. The new model is generally valid for halo and nonhalo transistors. It has been tested for several transistor types and technology nodes, showing a significantly increased accuracy. A measure for the halo impact on matching is given.

The 65nm tunneling field effect transistor (TFET) 0.68/spl mu/m/sup 2/ 6T memory cell and multi-V/sub th/ device

The tunneling field effect transistor (TFET) is fabricated using a 65nm standard CMOS process flow. The short-narrow TFET offers an on-current of 550/spl mu/A//spl mu/m which is comparable to the reference MOSFET device. Due to the integrated substrate/well contact the effective area of the TFET is smaller compared to the corresponding MOSFET. Thus, the size of a system-on-a-chip design is reduced by more than 5%. The quantum-mechanical TFET is able to extend the epoch of the CMOS technology by showing reduced short channel effects and smaller leakage currents. A multi-threshold TFET device is proposed which does not need additional implantation steps. A 0.68/spl mu/m/sup 2/ 6 transistor memory cell is fabricated using TFETs and MOSFETs showing the compatibility of MOSFET and TFET and a decrease of the memory array area of approximately 3%.