Cesar Garza

A novel contact hole shrink process for the 65-nm-node and beyond

Patterning of sub-100nm contacts for sub-90-nm-node devices is one of the primary challenges of photolithography today. The challenge involves achieving the desired resolution while maintaining manufacturable process windows. Increases in numerical aperture and reductions in target CDs will continue to shrink process windows and increase mask error factor resulting in larger CD variation. Several techniques such as RELACS, SAFIER, and resist reflow have been developed to improve the resolution of darkfield patterns such as contacts and trenches. These techniques are all post-develop processes applied to the patterned resist. Reflow is a fast process with low cost of ownership, but has two major disadvantages of high temperature sensitivity and large proximity bias. SAFIER and RELACS both have much slower throughput and higher cost of ownership than reflow. SAFIER also is sensitive to temperature and has large proximity bias. In this paper, a novel process is described that reduces the diameter of contact holes in resist up to 25nm without proximity effects. This process uniformly swells the resist film resulting in a shrink of patterned holes or trenches. Results are shown for 248nm and 193nm single layer resists, and a 193nm bilayer resist. This process has the potential to be high throughput with low cost of ownership similar to reflow techniques but without the proximity effects and thermal sensitivity observed with reflow.

Reduction of line edge roughness and post resist trim pattern collapse for sub 60 nm gate patterns using gas-phase resist fluorination

Resist pattern edge roughness is expected to cause degradation of transistor performance as gate lengths shrink below 40 nm. In the literature line edge roughness (LER) has been linked to many optical and chemical variables associated with the lithography process. As resist trim etch becomes more aggressive over time, LER on etched gates becomes less linked to the roughness in resist, and more to a product of the coupled lithography and etch processes. The aspect ratio of trimmed resist features increases and patterns become susceptible to pattern collapse, bending and tearing. Conversely if aspect ratios are maintained through the trim process, then the ability of the resist to protect the substrate from the final etch is degraded as the resist thickness decreases. A novel method of resist fluorination is presented that significantly reduces LER and pattern deformations such as collapse, tearing and bending. Experimental data shows that resist fluorination can make possible sub-30 nm etched polysilicon gates at aspect ratios on the order of 5:1. The same fluorination process yields LER improvements of 15% to 20% on average with largest improvements in the mid-range roughness frequencies of 10 - 50 μm-1. The length scale, or inverse of frequency, is also used in the study. The resist fluorination process is described as it is used in the study. Experimental and analytical data show how the process is reduced to practice and how LER and pattern deformation are improved. The fluorination process is simple to integrate into a standard wafer flow, has low cost of ownership, and yields large process improvements.

The study of phase-angle and transmission specifications of 6% att-EAPSM for 90nm, 65nm and 45nm node wafer manufacturing patterning process

6% attenuated embedded PSM (att-EAPSM) has been widely used in semiconductor wafer manufacturing industry at 130nm, 90nm, 65nm and 45nm nodes. To effectively use the 6% att-EAPSM photomask technology and reduce its manufacturing costs, it is important for the industry to develop a comprehensive mask specification that can fully meet the wafer level lithography requirements without over-constraining the control parameters in 6% att-EAPSM manufacturing process. In this paper, we used computer simulation software, Prolith by KLA-Tencor to study the impact of local phase-angle and transmission errors to wafer lithography process. The simulation results indicated that phase-angle and transmission errors result in a best focus plane shift, and hence reduce the common focus exposure window across the mask. The data also indicated that as the NA (numerical aperture) of the lithography system increases, the same amount of phase-angle error results less amount of focus shift. Based on this study and the practical common focus windows in semiconductor industry, we proposed a new phase-angle and transmission specification of 6% att-EAPSM for 90nm, 65nm and 45nm node wafer process.

Early look into device level imaging with beyond water immersion

The lithography prognosticator of the early 1980s declared the end of optics for sub-0.5&mgr;m imaging. However, significant improvements in optics, photoresist and mask technology continued through the mercury lamp lines (436, 405 & 365nm) and into laser bands of 248nm and to 193nm. As each wavelength matured, innovative optical solutions and further improvements in photoresist technology have demonstrated that extending imaging resolution is possible thus further reducing k1. Several author have recently discussed manufacturing imaging solutions for sub-0.3k1 and the integration challenges. Our industry will continue to focus on the most cost effective solution. What continues to motivate lithographers to discover new and innovative lithography solutions? The answer is cost. Recent publications have demonstrated sub 0.30 k1 imaging. The development of new tooling, masks and even photoresist platforms impacts cost. The switch from KrF to ArF imaging materials has a significant impact on process integration. This paper will focus on the usefulness of beyond water immersion for 22nm logic node. Data will be presented demonstrating the impact of higher refractive index photoresist systems have on the further extension of ArF Immersion.

Improved ion implantation masking through photoresist fluorination

As semiconductor gate lengths shrink, photoresist trends toward thinner films. Thick photoresist films are not desirable because they tend to absorb more light, require higher energies to pattern, increase pattern collapse, and subtract from depth of focus and exposure latitude. The minimum thickness of implant photoresist is governed by the stopping power of the photoresist for the ion type and the energy of the implant. Relatively high energy implants and/or lower ion stopping power in the photoresist require thicker photoresist films. These problems can be mitigated through a novel photoresist fluorination process. The fluorination process results in the replacement of H atoms by heavier F atoms effectively increasing the molecular weight of the fluorinated film and its ability to block ion implantation. This straightforward and cost-effective process is investigated for use with a standard 248 nm dyed photoresist. Substrate damage probe measurements and Secondary Ion Mass Spectrometry depth profiles show species-dependent ion implant masking improvements of up to 40 % for fluorinated photoresist versus as-developed photoresist. Geometric and process margin arguments are discussed for thinning photoresist where angled implants are needed or process capability is insufficient. Finally, electrical data is presented that demonstrates the manufacturability of these fluorinated and thinned photoresist films.