Richard D. Peters

Critical dimension control in optical lithography

The exposure tool used for integrated circuit (IC) fabrication is critical to improving the packing density and transistor speed of the circuits. In addition to increasing resolution, which improves packing density and transistor speed, the exposure tool is also expected to provide tight linewidth control across the chip. Across chip linewidth variation (ACLV) has a significant influence on circuit speed. The allowed ACLV is usually assumed to be about 10% of the nominal linewidth. Therefore, just a few nanometers in linewidth variation may significantly impact IC performance. Contributions to the CD variation across chip and wafer due to lithographic sources of error are discussed in this paper. CD control afforded by future optical lithography tools is estimated using Monte Carlo aerial image simulations by making reasonable assumptions about the performance of the future tools and mask CD control. The impact of reticle enhancement technologies on ACLV is evaluated. The main sources of CD error can be identified. This approach will help define the path to improving CD control. The technique described was tested using data from the current generation of technology, and reasonable agreement between predicted and observed CD variation was obtained.

Integration of UTR processes into MPU IC manufacturing flows

Low-k1 imaging, high-NA optics, pattern collapse, and the absorption of resist materials in 157-nm and EUV lithographies are driving down the thickness of the photoresist layer in integrated circuit fabrication processes. Although devices and test structures have been successfully fabricated with resist films thinner than 160 nm on various levels, the fabrication of working devices with high yield using ultrathin resist (UTR) integrations on multiple device layers has yet to be demonstrated. In the present work, gates have been patterned with 140-nm thick resist films with 10-15 defects per wafer, none of which are specific to the UTR process. Similar UTR gates were also patterned over 80-nm steps with no defects associated with the topography. The UTR NMOS transistors in this work have 10 pA/micrometers leakage and 400 (mu) A/micrometers drive currents, but the PMOS transistors do not perform as well. The line-edge roughness (LER) is 5-8 nm 3(sigma) depending upon exposure mask (binary vs. PSM) and substrate. Etching into 100 nm of crystalline Si reduces the LER to 4-7 nm 3(sigma) . The power spectral densities of the roughness have a Lorentzian shape, and most of the roughness occurs over length scales larger than 100 nm. Contact chains with electrical characteristics comparable to standard processes were fabricated with 120-nm thick resist films. Polysilicon as thick as 150 nm was etched successfully with 80-nm thick resist films and hardmasks.

Development and characterization of 193-nm ultra-thin resist process

The lithographic performance of a single layer 193nm resist platform, Sumitomo PAR707, was evaluated for 100nm node patterns for thicknesses ranging from 313nm to 60nm. We first demonstrated that the standard resist formulation could not be used for sub-200nm thicknesses because of unacceptable line edge roughness (LER). We then evaluated the influence of the concentration of photo acid generator (PAG) in the resist formulation of LER over the thickness range of 313nm to 60nm. High PAG loading was found to decrease LER significantly for sub-200nm thicknesses. Using the optimal formulation for minimal LER for a given thickness, process latitudes for 100nm node patterns were determined. The overall dose-focus latitudes were found to remain very close for all thicknesses, with slightly larger latitude for thicker imaging layers.

Single-layer and bilayer resist processes for EUV-type integrations

The high absorption of extreme ultraviolet (EUV) radiation by all materials necessitates the use of thin photoresist films with thicknesses less than 200 nm for EUV lithography to ensure good imaging. Thinning the resist thickness below 150 nm or even 100 nm may produce benefits such as increased sensitivity, larger process latitude, and increased resolution. However, these potential benefits as well as the required need for thin resists come at the expense of reduced etch resistance. EUV lithography will require the use of some type of thin imaging technique such as top-surface imaging, bilayer resists, or single layer resists with hardmasks in order to achieve the necessary etch resistance. In this paper, we discuss results that demonstrate the feasibility of using thin resist approaches for fabricating working devices. We have successfully fabricated working 130-nm-node SRAMs using a single layer 248 nm ultrathin resist (< 150-nm-thick) with a hardmask for both gate and contact layers on the same wafer. This result represents the first demonstration of working devices fabricated using ultrathin resists on multiple device layers. We also present initial patterning experiments using a 193 nm bilayer resist for brightfield applications such as the gate layer, and compare imaging performance to that of a 193 nm single layer resist. The advantages and disadvantages of the single layer and bilayer approaches are discussed.

Controlling line-edge rougness to within reasonable limits

The 2001 edition of the International Technology Roadmap for Semiconductors establishes line-edge roughness (LER) requirements for patterned resist lines. Little is known, however, about how LER affects device performance or about how much LER is acceptable for a given technology. Our work seeks to answer these questions by combining process modeling, three-dimensional (3D) device modeling, and experiment to investigate the amount of LER that can be varied by process conditions and the levels to which LER must be controlled. Our process models show the expected trade-offs between resist diffusion, LER, and resolution, and they show that much of the high-frequency, high-amplitude roughness can be reduced through appropriate etch and implant diffusion processes. The low-frequency roughness, on the other hand, is much harder to eliminate. Experimentally, we have found that the aerial image quality and the etch process have the largest effect on the edge roughness transferred to polysilicon lines, and the roughness after etch is distributed over a broad range of frequencies. The 3D device models indicate that the amount of roughness that gets transferred to the junctions will dominate the electrical behavior, and the effects will likely be different for PMOS devices than NMOS devices.

The application of CPL reticle technology for the 0.045-mm node

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.

Process latitude measurements and their implications for CD control in EUV lithography

We have exposed 10 wafers on the Engineering Test Stand (ETS), the 0.1 NA EUV scanner at Sandia National Laboratories in Livermore, CA. The EUV reflective mask was fabricated in-house using a Ta-based absorber stack on Mo/Si multilayers. The printed wafers contained different line sizes and pitches, line-end shortening measurement structures, contact holes, and patterns for estimating absorber defect printability. The depths of focus of each feature are typically 2 um due to the small NA of the scanner, and these should decrease by at least a factor of 6.25 as the NAs increase to 0.25. The data from measurements of line size through pitch and line-end shortening test structures indicate that both 1D and 2D optical proximity correction will be required. Defects that are either notches in or protrusions from absorber lines are the first to print, and they begin to print when they reach approximately 15~nm (1X) in size. This size threshold is in accordance with the 2003 ITRS specifications. We also report the first printing of SRAM bitcells with EUV lithography.

Ultrathin photoresists for 193-nm lithography

Fabrication of integrated circuits with sub-100 nm features will require tight control of critical dimensions, line edge roughness, and profiles of patterned features. The drive to smaller features will be accomplished principally by reduction of exposure wavelength in lithography systems. The use of 157 nm and EUV lithography will most likely require thin resists with thicknesses less than 150 nm due to the high absorption of materials at these wavelengths. High NA and low k1 systems for 193 nm lithography may also benefit from the use of thin photoresist processes. The properties and behavior of thin resists are expected to be strongly affected by interfaces, and thus, the lithographic performance of resists with sub-200-nm thickness is of interest. In this paper, we present a study of the lithographic behavior of a single layer 193 nm resist at different thicknesses ranging from 90 nm to 240 nm. The line edge roughness (LER) of 193 nm resist films increased dramatically with decreasing film thickness, but increasing the concentration of photoacid generator (PAG) and base quencher in the films helped reduce the LER. The process latitude for dense 110 nm lines (250 nm pitch) imaged using a single resist formulation with high PAG/quencher concentration was experimentally determined for 4 thicknesses (90 nm to 240 nm) by changing only the spin speed. The process latitude was found to be almost equivalent for sub-200 nm thick films, however, sub-100 nm thick films exhibited much higher LER than the thicker resist films. The performance of the 193 nm resist was compared to a 248 nm resist coated at thicknesses ranging from 104 nm to 260 nm. The 248 nm resist exhibited a decreasing trend in both exposure latitude and depth of focus with decreasing film thickness. Time-of-flight secondary ion mass spectrometry was used to investigate the distribution of PAG in the resist films. Some of the resist behavior of sub-150 nm thick films could be explained due to non-uniform PAG distribution.

CPL reticle technology for advanced device applications

Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RETs). The race to smaller and smaller geometrys has forced device manufacturers to k1s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.

Fabrication of integrated circuits with high yield using ultra-thin resist processes

We have demonstrated the fabrication of working 130 nm-node SRAMs with high yield using single layer ultra-thin resist (UTR) integrations. Transistor gates were fabricated using 140-nm-thick resist films in combination with a single layer, inorganic anti-reflective coating (ARC) that also acted as a hardmask (HM). An aggressive ARC/HM removal process was developed to enable the use of a thick ARC/HM. The thick ARC/HM was necessary to allow the incorporation of a resist trim step prior to polysilicon gate etch that reduced the transistor gate lengths in silicon from the printed critical dimension (CD) in resist. Transistor performance for both NMOS and PMOS devices with UTR-fabricated gates was equivalent to the performance of standard transistors. Working SRAM arrays were fabricated using UTR at the gate layer that achieved natural yield within 10% of the yield achieved with a thick resist process, and in some cases, with yield that exceeded the thick resist process. CD control for the UTR gate photo process was equivalent to the baseline photo process, and the UTR gate photo process was optimized to increase device yield. Contacts fabricated using 120-nm-thick resist films exhibited electrical characteristics equivalent to those fabricated with standard processes, and yielding SRAM devices were fabricated using UTR at the contact layer. Defect inspection of UTR contact patterning detected the formation of pinholes in the UTR films; however, the formation of pinholes was found to be dependent upon substrate-resist interactions.