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Dive into the research topics where Stanley M. Filipiak is active.

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Featured researches published by Stanley M. Filipiak.


Advances in resist technology and processing. Conference | 2005

A novel contact hole shrink process for the 65-nm-node and beyond

Richard D. Peters; Patrick Montgomery; Cesar Garza; Stanley M. Filipiak; Tab A. Stephens; Dan Babbitt

Patterning of sub-100nm contacts for sub-90-nm-node devices is one of the primary challenges of photolithography today. The challenge involves achieving the desired resolution while maintaining manufacturable process windows. Increases in numerical aperture and reductions in target CDs will continue to shrink process windows and increase mask error factor resulting in larger CD variation. Several techniques such as RELACS, SAFIER, and resist reflow have been developed to improve the resolution of darkfield patterns such as contacts and trenches. These techniques are all post-develop processes applied to the patterned resist. Reflow is a fast process with low cost of ownership, but has two major disadvantages of high temperature sensitivity and large proximity bias. SAFIER and RELACS both have much slower throughput and higher cost of ownership than reflow. SAFIER also is sensitive to temperature and has large proximity bias. In this paper, a novel process is described that reduces the diameter of contact holes in resist up to 25nm without proximity effects. This process uniformly swells the resist film resulting in a shrink of patterned holes or trenches. Results are shown for 248nm and 193nm single layer resists, and a 193nm bilayer resist. This process has the potential to be high throughput with low cost of ownership similar to reflow techniques but without the proximity effects and thermal sensitivity observed with reflow.


international interconnect technology conference | 2002

Interconnect mechanical reliability with low /spl kappa/ dielectric as final ILD

Cindy Goldberg; Lei L. Mercado; Stanley M. Filipiak; Stephen Crown

The use of low /spl kappa/ materials as the final intralayer dielectric (ILD) layer can impact the integrity of edge seals, blown fuses, and even the interface integrity at lower levels. Furthermore, the influence of the final ILD on lower levels depends on the total number of metal levels in the product. This paper addresses the role of final ILD in both environmental and package reliability, and the use of predictive modeling of mechanical reliability.


Archive | 2003

Method for forming a semiconductor device and structure thereof

Cindy K. Goldberg; Stanley M. Filipiak; John C. Flake; Yeong-Jyh T. Lii; Bradley P. Smith; Yuri E. Solomentsev; Terry G. Sparks; Kirk J. Strozewski; Kathleen C. Yu


Archive | 2006

Method for forming a stressor structure

Mark D. Hall; Rode R. Mora; Michael D. Turner; Laegu Kang; Toni D. Van Gompel; Stanley M. Filipiak


Archive | 2006

Method of forming an interlayer dielectric

Paul A. Grudowski; Stanley M. Filipiak; Yongjoo Jeon; Chad E. Weintraub


Archive | 2002

Method for forming a passivation layer for air gap formation

Cindy K. Goldberg; Stanley M. Filipiak; John C. Flake; Yeong-Jyh T. Lii; Bradley P. Smith; Yuri E. Solomentsev; Terry G. Sparks; Kirk J. Strozewski; Kathleen C. Yu


Archive | 2002

Method for forming a passivation layer for air gap formation and structure thereof

Cindy Goldberg; Stanley M. Filipiak; John C. Flake; Yeong-Jyh T. Lii; Bradley P. Smith; Yuri E. Solomentsev; Terry Sparks; Kirk J. Strozewski; Kathleen C. Yu


Archive | 2005

Method of forming a semiconductor device having a diffusion barrier stack and structure thereof

Lynne M. Michaelson; Edward Acosta; Ritwik Chatterjee; Stanley M. Filipiak; Sam S. Garcia; Varughese Mathew


Archive | 2005

Method of making a semiconductor device using treated photoresist

Cesar Garza; William D. Darlington; Stanley M. Filipiak; James E. Vasek


Archive | 2006

PLASMA ENHANCED NITRIDE LAYER

Jian Chen; Stanley M. Filipiak; Yongjoo Jeon; Tab A. Stephens

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John C. Flake

Louisiana State University

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Cesar Garza

Freescale Semiconductor

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