Cezar Reinbrecht

Gossip NoC – Avoiding Timing Side-Channel Attacks through Traffic Management

The wide use of Multi-processing systems-on-chip (MPSoCs) in embedded systems and the trend to increase the integration between devices have turned these systems vulnerable to attacks. Malicious software executed on compromised IP may become a serious security problem. By snooping the traffic exchanged through the Network-on-chip (NoC), it is possible to infer sensitive information such as secrets keys. NoCs are vulnerable to side channel attacks that exploit traffic interference as timing channels. When multiple IP cores are infected, they can work coordinately to implement a distributed timing attack (DTA). In this work we present for the first time the execution of a DTA and a secure enhanced NoC architecture able to avoid the timing attacks. Results show that our NoC proposal can avoid the DTA with an increase of only 1% in area and 0.8% in power regarding the whole chip design.

Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip

Application-specific network-centric architectures (such as Networks on-Chip, NoCs) have recently become an effective solution to support high bandwidth communication in Multiprocessor Systems-on-Chip (MPSoCs). Moreover, the introduction of the hierarchy concept in the NoC design benefits from the main locality nature of the communication in MPSoC architectures. This paper presents a methodology to design Application Specific Hierarchical NoC (ASHiNoC) architectures considering foorplanning information. The presented approach targets heterogeneous clustered architectures where the intra-cluster communication is managed by a low-latency circuit-switched crossbar, while the inter-cluster communications are managed by a high-bandwidth packet-based NoC, allowing regulars topologies. The proposed design flow faces the problem by starting from the cluster selection down-to the foorplanning-aware estimation of the interconnect performances in terms of latency, power, area within each cluster and for the backbone NoC. Experimental results show that the AHiNoC architecture is able to guarantee an interconnection power and latency reduction of 49% and 33% respectively, at a cost of an area increment of 78% with respect to a flat topology version.

Side channel attack on NoC-based MPSoCs are practical: NoC prime+probe attack

Many authors have shown how to break the AES cryptographic algorithm with side channel attacks, specially the timing attacks oriented to caches, like Prime+Probe. In this paper, we present a practical timing attack on NoC that improves Prime+Probe technique. Our attack targets the communication between an ARM Cortex-A9 core and a shared cache memory. Furthermore, we evaluate a secure enhanced NoC applied as a countermeasure of the timing attack. Finally, we demonstrate that attacks on MPSoCs through the NoC are a real threat and need to be further explored.

Floorplan-aware hierarchical NoC topology with GALS interfaces

Networks-on-chip has been seen as an interconnect solution for complex systems. However, performance and energy issues still represent limiting factors for Multi-Processors System-on-Chip (MPSoC). Complex router architectures can be prohibitive for the embedded domain, once they dissipate too much power and energy. In this paper we propose a low power hierarchical network topology with GALS interfaces, allowing each cluster operates in a specific frequency. The clusters are composed by crossbar devices and the number of cores allocated for each cluster is defined considering floorplan information. Experimental results show that our strategy can reduce the power dissipation in up to 58% and the latency in up to 56% for the benchmarks analyzed when compared with a packet-switched mesh network-on-chip.

DHyANA: A NoC-based neural network hardware architecture

Understanding and modeling the brain is one of the key scientific challenges in the twenty-first century, and a grown effort is rising on a global scale. Due to its high parallelism, the hardware implementation of large-scale spiking neural networks (SNNs) promises superior execution speed compared to sequential software approaches. Such systems can significantly benefit from the use of networks-on-chip(NoC), as they scale very well concerning area, performance, power/energy consumption, and overall design effort. We developed a hierarchical network-on-chip for a hardware SNN architecture to improve the communication and scalability of the system. The architecture was implemented in an Altera Stratix IV FPGA, and a logic synthesis was performed to evaluate the system, achieving an area of 0.23mm2 and a power dissipation of 147mW for a 256 neurons implementation.

PHiCIT: Improving Hierarchical Networks-on-chip through 3D Silicon Photonics Integration

The Network-on-Chip (NoC) architecture has been seen as an interconnect solution for complex systems. However, performance and energy issues still represent limiting factors for Multi-Processors Systems-on-Chip (MPSoC). In order to match low power and high performance, hierarchical NoCs have been proposed, with interconnecting clusters of IPs tailored to application specific domains. In the near future however, this methodology will be limited by the long wires for global connection. In this paper, we present an optimized hierarchical network-on-chip, the PHiCIT (Photonic Hierarchical Crossbar-based Interconnection Three-dimensional architecture). This architecture proposal aims to maximize the overall performance by using three levels of interconnection: photonic crossbars for intra-cluster communication, traditional electric routers for the inter-cluster communication, and 3D technology to explore power and area optimization. Experimental results show that PHiCIT can reduce the latency against a pure electrical mesh NoC by up to 47%, against an electric hierarchical NoC by up to 6%, and against a photonic mesh NoC by up to 34%, considering PARSEC benchmark applications.

A power-efficient hierarchical network-on-chip topology for stacked 3D ICs

Multi-Processors Systems-on-Chip (MPSoCs) are demanding for high performance, low power and high density, and therefore, three-dimensional integrated circuits (3DIC) emerge as a solution to integrate these systems. In order to appropriately interconnect the layers of these systems in terms of flexibility and scalability, a Network-on-Chip (NoC) is typically employed. In this paper, we argue about the scenario of 3D designs, covering all important issues about this new concept. In agreement with all features discussed in this paper, we have proposed a hierarchical 3D topology that meets well the reality of these designs. Experimental results analyze different topologies and show the large benefits in area and power of our proposal.

Hierarchical and multiple switching NoC with floorplan based adaptability

The Networks-on-Chip paradigm has been seen as an interconnect architecture solution for complex systems. However, performance and energy issues still represent limiting factors for Multi-Processors System-on-Chip. Moreover, the execution of different applications requires flexible and transparent interconnection solutions, and this feature is best provided by a selfadaptable system. In this paper we propose HASIN, an architecture that explores the suitable switching architecture according to the traffic in each region of the system, in a hierarchical manner. The proposed interconnection allows adapting the network at runtime using three switching possibilities to reconfigure itself according to the floorplan information. HASIN allows increasing the throughput up to 77% and reducing the power consumption up to 76% when compared to a packet-switched mesh network-on-chip.

Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection

Many authors have shown how to break the AES cryptographic algorithm with side channel attacks; specially the timing attacks oriented to caches, like Prime+Probe. In this paper, we present two practical timing attacks on NoC that improve Prime+Probe technique, the P+P Firecracker, and P+P Arrow. Our attacks target the communication between an ARM Cortex-A9 core and a shared cache memory. Furthermore, we evaluate a secure enhanced NoC as a countermeasure against the timing attack. Finally, we demonstrate that attacks on MPSoCs through the NoC are a real threat and need to be further explored.

Adaptive multiple switching strategy toward an ideal NoC

The exigency for heterogeneous many-core systems has brought an exponential growth in the complexity of their interconnections. In this manner, other Network-on-Chip (NoC) alternatives are being sought to attend the requirements in terms of power consumption and performance. Nevertheless, several of these proposals present very complex architectures, with virtual channels, tables and extra controls. In this paper we propose the junction of two advantageous strategies: hierarchical topology with adaptability. The use of these two techniques is novel in the literature and it allows ensuring high performance even when the application has their communication rates altered. The gains in power and in performance are possible due to the use of low cost components in a hierarchical structure.