Martha Johanna Sepúlveda

NoC-Based Protection for SoC Time-Driven Attacks

Systems-on-chip (SoCs) based on many core architectures can be attacked. Malicious processes can infer secrets from on-chip sensible traffic by evaluating the degradation on their communication performance. Such a threat rises from the resource sharing. In order to avoid such time-driven attacks, the network-on-chip (NoC) can integrate mechanisms to isolate different communication flows. In this letter, we propose two mechanisms, random arbitration and adaptive routing, that dynamically allocate the SoC resources to avoid such attacks. We compare our approach to the unique previous work under several traffic conditions. We demonstrate that our mechanisms are effective to protect the SoC while increasing the overall performance.

Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip

Next to performance, it becomes increasingly important that Networks-on-Chip (NoCs) also provide security features such as access control, authentication and availability. They are usually implemented by firewalls at the network interfaces (NIs) of the processing elements (PEs). This paper provides a more efficient way to integrate these security requirements into application-specific NoCs by inserting firewalls also between NoC routers. This approach helps to reduce the communication overhead required for the security information in the packet headers, which can consume 3% to 9% of the total communication bandwidth. It is challenging to manually find the optimal firewall configuration because an application-specific NoC has an irregular topology, which is customized for certain known application, e.g. a smartphone chip. Thus, we show how to automatically solve this problem by formulating it as an Integer Linear Programming (ILP) problem. The solution results in firewall positions such that the communication overhead is minimized and all given security requirements are satisfied. Experiments are performed on two industrial system specifications. Compared to the solution with the firewalls at the NIs, communication overhead is reduced by up to 63%. The optimization only takes a few seconds for a standard ILP solver.

Scalable NoC-based architecture of neural coding for new efficient associative memories

We present the first NoC-based hardware implementation of Neural Coding (NC), which is a new approach that opens outstanding perspectives for the design of associative memories and learning machines. We first propose optimized architectures of memories and processing elements that allow for an efficient distributed implementation. Then we introduce different NoC architectures to interconnect all elements, it provides the required scalability and takes advantage of parallel transfer opportunities. Performance, cost and energy consumption tradeoffs of various NoC solutions are compared and discussed. Based on previous implementation results, we run SystemC-TLM that validate the behavior of the algorithm and of the efficiency of the dedicated architecture. This work demonstrates that this architecture can meet expected requirements in terms of scalability and hierarchy, and consequently that NC-based architectures are compliant with efficient hardware implementations of a new and promising model of associative memories.

Notifying memories: a case-study on data-flow applications with NoC interfaces implementation

NoC-based architectures overcome the limitations of traditional buses by exploiting parallelism and offer large band-widths. NoC adoption also increases communication latency, which is especially penalising for data-flow applications (DF). We introduce the notifying memories (NM) concept to reduce this overhead. Our original approach eliminates useless memory requests. This paper demonstrates NM in the context of video coding applications implemented with dynamic DF. We have conducted cycle accurate systemC simulation of the NoC on an MPEG4 decoder to evaluate NM efficiency. The results show significant reductions in terms of latency (78%), injection rate (60%), and power savings (49%) along with throughput improvement (16%).

Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping

Current SoC (System-on-Chip) are characterized by the integration of larger amount of IPs targeting a wide range of application fields. Such multi-application systems are constrained by a set of security and performance requirements. Network-on-chip (NoC) is becoming important as the communication structure of the SoC. IP mapping is one of the most critical parameters in NoC design, strongly influencing the SoC performance. IP mapping has been solved for single application systems using single and multi-objective optimization algorithms. In this paper we propose the use of a multi-objective adaptive immune algorithm (M2AIA), an evolutionary approach to solve the multi-application NoC mapping problem targeting security issues, in order to group the IPs according the security characteristics while achieving the best performance. Latency and power consumption were adopted as the target multi-objective functions constrained by the security function. To compare the efficiency of our approach, our results are compared with those of the genetic and branch-and-bound multi-objective mapping algorithms. The experimental results showed that the M2AIA achieves configurations that fulfill the security requirements while decreasing the power consumption in 27% and the latency in 42% compared to the branch-and-bound approach and 29% and 36% over the genetic approach.

PHiCIT: Improving Hierarchical Networks-on-chip through 3D Silicon Photonics Integration

The Network-on-Chip (NoC) architecture has been seen as an interconnect solution for complex systems. However, performance and energy issues still represent limiting factors for Multi-Processors Systems-on-Chip (MPSoC). In order to match low power and high performance, hierarchical NoCs have been proposed, with interconnecting clusters of IPs tailored to application specific domains. In the near future however, this methodology will be limited by the long wires for global connection. In this paper, we present an optimized hierarchical network-on-chip, the PHiCIT (Photonic Hierarchical Crossbar-based Interconnection Three-dimensional architecture). This architecture proposal aims to maximize the overall performance by using three levels of interconnection: photonic crossbars for intra-cluster communication, traditional electric routers for the inter-cluster communication, and 3D technology to explore power and area optimization. Experimental results show that PHiCIT can reduce the latency against a pure electrical mesh NoC by up to 47%, against an electric hierarchical NoC by up to 6%, and against a photonic mesh NoC by up to 34%, considering PARSEC benchmark applications.

Side-channel attack resilience through route randomisation in secure real-time Networks-on-Chip

Security can be seen as an optimization objective in NoC resource management, and as such poses trade-offs against other objectives such as real-time schedulability. In this paper, we show how to increase NoC resilience against a concrete type of security attack, named side-channel attack, which exploit the correlation between specific non-functional properties (such as packet latencies and routes, in the case of NoCs) to infer the functional behaviour of secure applications. For instance, the transmission of a packet over a given link of the NoC may hint on a cache miss, which can be used by an attacker to guess specific parts of a secret cryptographic key, effectively weakening it. We therefore propose packet route randomization as a mechanism to increase NoC resilience against side-channel attacks, focusing specifically on the potential impact of such an approach upon hard real-time systems, where schedulability is a vital design requirement. Using an evolutionary optimization approach, we show how to effectively apply route randomization in such a way that it can increase NoC security while controlling its impact on hard real-time performance guarantees. Extensive experimental evidence based on analytical and simulation models supports our findings.

NoC-MRAM architecture for memory-based computing: Database-search case study

The paper presents a novel flexible low-power architecture for memory-based computing that relies on a NoC and power-gated distributed MRAM. The proposed approach is demonstrated with a database search application implemented with a Sparse-Neural-Network (SNN). Multiple SystemC simulations have been conducted over the MRAM-based computing architecture targeting hundreds of database queries. The results show hit rates of about 95%, impressive power gains compared to SRAM, and significant impact of power-gating. The results also provide an evidence on the feasibility of using power-gated MRAM associated with a NoC as a solution for low power implementation of memory-based computing.

Network Contention-Aware Method to Evaluate Data Coherency Protocols within a Compilation Toolchain

Shared memory is a critical issue for large distributed systems. Despite several data coherency protocols have been proposed, the selection of the protocol that best suits to the application requirements and system constraints remains a challenge. The development of multi-coherency systems, where different protocols can be deployed during runtime, appears to be an interesting alternative. In order to explore the design space of the coherency protocols a fast and accurate method should be used. In this work we rely on a compilation toolchain that transparently handles data coherency decisions for a multi-protocol platform. We focus on the analytical evaluation of the coherency configuration that stands within the optimization loop. We propose to use a TLM NoC simulator to get feedback on expected network contentions. We evaluate the approach using five workloads, three data coherency protocols and two NoC topologies. As a result, we are able to obtain a fast and accurate evaluation of the different coherency-protocol alternatives.

3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mapping

Three dimensional Multiprocessor System-on-Chip (3D-MPSoC) are characterized by the integration of a large amount of hardware components targeting a wide range of application on a single chip. However, heating is one of the major pitfalls of the 3D-MPSoCs. Three dimensional Network-on-Chip (3D-NoC) is used as the communication structure of the 3D-MPSoC. Its main role in the system operation and performance turns critical the optimal 3D-NoC design. Mapping is one of the most critical 3D-NoC parameters, strongly influencing the 3D-MPSoC performance. In this paper we propose the use of a multi-objective immune algorithm (3DMIA), an evolutionary approach to solve the multi-application 3D-NoC mapping problem. Latency and power consumption were adopted as the target multi-objective functions constrained by the heating function. Final 3D-NoC configurations enhance up to 73% the power and 42% the latency when compared to the previous reported results. We also evaluate the effect on the mutation rate and population size on the convergence speed of 3DMIA. We find that the adaptive mutation rate increases the performance of 3DMIA up to 84% when compared to static mutation rate approach.