Luigi Carro

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

Triple modular redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections between signals from distinct redundant logic parts, which can generate an error in the output. This paper investigates the optimal design of the TMR logic (e.g., by cleverly inserting voters) to ensure robustness. Four different versions of a TMR digital filter were analyzed by fault injection. Faults were randomly inserted straight into the bitstream of the FPGA. The experimental results presented in this paper demonstrate that the number and placement of voters in the TMR design can directly affect the fault tolerance, ranging from 4.03% to 0.98% the number of upsets in the routing able to cause an error in the TMR circuit.

Making Java work for microcontroller applications

The authors investigate complete system development using a Java machine aimed at FPGA devices. A new design strategy targets a single FPGA chip, within which the dedicated Java microcontroller-FemtoJava-is synthesized.

Designing fault-tolerant techniques for SRAM-based FPGAs

FPGAs have become prevalent in critical applications in which transient faults can seriously affect the circuits operation. We present a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison (DWC) and concurrent error detection (CEO) to provide a highly reliable circuit while maintaining hardware, pin, and power overheads far lower than with classic triple-modular-redundancy techniques.

Designing fault tolerant systems into SRAM-based FPGAs

This paper discusses high level techniques for designing fault tolerant systems in SRAM-based FPGAs, without modification in the FPGA architecture. Triple Modular Redundancy (TMR) has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications. However, TMR comes with high area and power dissipation penalties. The new technique proposed in this paper was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. We present some fault coverage results and a comparison with the TMR approach.

Analyzing area and performance penalty of protecting different digital modules with Hamming code and triple modular redundancy

This work compares two fault tolerance techniques, Hamming code and triple modular redundancy (TMR), that are largely used to mitigate single event upsets in integrated circuits, in terms of area and performance penalty. Both techniques were implemented in VHDL and tested in two target applications: arithmetic circuits with pipeline and registers files. Area overhead results show that TMR is more appropriated for modules using single registers like in pipelines, control and datapath circuits, while Hamming code is a better trade-off for groups of registers, such as register files, caches and embedded memories.

The impact of NoC reuse on the testing of core-based systems

The authors propose the reuse of on-chip networks for the test of core-based systems that use this platform. Two possibilities of reuse are proposed and discussed with respect to test time minimization. An algorithm exploiting network characteristics to reduce test time is presented. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.

Time and energy efficient mapping of embedded applications onto NoCs

This work analyzes the mapping of applications onto generic regular networks-on-chip (NoCs). Cores must be placed considering communication requirements, so as to minimize the overall application execution time and energy consumption. We expand previous mapping strategies by taking into consideration the dynamic behavior of the target application and thus potential contentions in the intercommunication of the cores. Experimental results for a suite of 22 benchmarks and various NoC sizes show that a 42% average reduction in the execution time of the mapped application can be obtained, together with a 21% average reduction in the total energy consumption for state-of-the-art technologies.

Transparent reconfigurable acceleration for heterogeneous embedded applications

Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in a single device. Although reconfigurable architectures have already shown to be a potential solution for such systems, they just present significant speedups of very specific dataflow oriented kernels. Furthermore, reconfigurable fabric is still withheld by the need of special tools and compilers, clearly not sustaining backward software compatibility. In this paper, we propose a new technique to optimize both dataflow and control-flow oriented code in a totally transparent process, without the need of any modification in the source or binary codes. For that, we have developed a Binary Translation algorithm implemented in hardware, which works in parallel to a MIPS processor. The proposed mechanism is responsible for transforming sequences of instructions at runtime to be executed on a dynamic coarse-grain reconfigurable array, supporting speculative execution. Executing the MIBench suite, we show performance improvements of up to 2.5 times, while reducing 1.7 times the required energy, using trivial hardware resources.

A study on communication issues for systems-on-chip

Present days cores composing a system-on-chip might be interconnected by means of both dedicated channels or shared buses. Nevertheless, future systems will have strong requirements on reusability and communication performance, which will constrain the use of such interconnect systems. An emerging approach, the networks-on-chip (NOCs), will potentially fulfill those requirements, because NOCs are reusable and their communication performance gracefully scales with the system growth. However, it is still not clear when the use of NOCs will become mandatory. This work introduces some studies to define the switching point when NOCs become the preferred communication architecture. A bus and a NOC are modeled and compared by using a set of mathematical models.

Distributed real-time embedded systems: Recent advances, future trends and their impact on manufacturing plant control

Real-time and embedded systems have historically been small scale. However, advances in microelectronics and software now allow embedded systems to be composed of a large set of processing elements, and the trend is towards significant enhanced functionality, complexity, and scalability, since those systems are increasingly being connected by wired and wireless networks to create large-scale distributed real-time embedded systems (DRES). Such embedded computing and information technologies have become at the same time an enabler for future manufacturing enterprises as well as a transformer of organizations and markets. This paper discusses opportunities for using recent advances in the DRES area in the deployment of intelligent, adaptive, and reconfigurable manufacturing plant control architectures. # 2007 Elsevier Ltd. All rights reserved.