Cezary Maj

Analysis of the effectiveness of core swapping in modern multicore processors

One of the interesting thermal management techniques for multi-core processors is core swapping. In this paper, using the published power data and floorplans for two modern high-performance processors, we employ the well-known HotSpot tool to perform the thermal simulation of the core swapping mechanism. Our transient simulations show that by using core swapping technique, it was possible to either minimize the hot spot temperature in the Ivy Bridge chip by 5°C or increase the operating frequency by 17% and maintain the same temperature as in the case without core swapping. We also derive an analytical model of the activity migration mechanism between two cores which may serve as a tool to calculate the swapping frequency given the desired maximal temperature drop. The model also allows for the correlation of the cooling effectiveness with the performance penalty induced by the swapping.

New methodology for thermal analysis of multi-core processors based on dedicated ASIC

Abstract Accurate prediction of thermal phenomena occurring in multi-core processors manufactured in new technologies prove to be both crucial and challenging. Therefore, in this paper, we introduce a new methodology for thermal analysis of such chips. The novelty of our approach is the use of a dedicated ASIC ( Application-Specific Integrated Circuit ), composed of a 16×24 array of heat cells, which emulates the power dissipation in a real processor and allows observing the chip temperature distribution in real-time. The ASIC takes as an input the power trace computed by the execution of benchmarks on a cycle-accurate processor simulator. The entire methodology flow is thoroughly described in the paper, including the details about the chip design and power modeling techniques. Post-layout simulations of our ASIC are used to verify the correctness of the design, whereas our approach to power modeling is validated using preliminary thermal simulations performed with existing software tools.

The evolution of MEMS and modelling methodologies

Purpose – The purpose of this paper is to show the evolution of microsystems together with modeling methods in the space of dozen years as a result of finished research in the frame of several projects.Design/methodology/approach – In this paper several approaches are presented. First, microsystems were built in multi project wafer technology. They were demonstrators like micromotor, micromirrors or micropumps modeled using dedicated design tool. A multi purpose chip was also designed using HDL description and FEM simulations. The next project concerned chemical sensors, where specialized models were developed and implemented in VHDL‐AMS in order to perform multidomain behavioral simulations. Dedicated tools were also developed for medical applications.Findings – The evolution of MEMS technology is strictly connected with simulation and modeling methods. The success and short time to market need fast and accurate simulation methods. This paper shows that the approach depends on application. Moreover, it i...

Coupled thermo-fluidic simulation for design space exploration of microchannels in liquid-cooled 3D ICs

Integrated liquid cooling is a promising idea for future 3D integrated circuits and potentially a scalable solution for ever-increasing power dissipation. In this paper, we analyze the efficiency of heat removal from a 3D stacked chip with microchannels. We build a detailed chip model and perform a coupled thermo-fluidic finite element method simulation for various microchannel designs. We explore the design space and point out the correlations between various chip and cooling parameters. In particular, we show that with ten microchannels of size 500 μm × 70 μm it is possible to remove 100 W of heat from a two-tier 3D chip while maintaining the temperature below 90°C and the pressure drop below 50 kPa.

Cache leakage power estimation using architectural model for 32 nm and 16 nm technology nodes

The constant increase of subthreshold current of nanometer transistors due to technology scaling may hinder the evolution of high-performance chips in the near future. This evokes the need of accurate leakage power modeling for new nanometer technologies. In this paper, we present an improved subthreshold current model, which was integrated it into an architectural-level power simulator. Using this simulator, we estimated the leakage power in a 2 MB cache memory for 32 nm and 16 nm technology nodes. Our results show that the cache leakage power dissipation for 2 MB 2-way cache at 100°C fabricated in the 32 nm technology is around 1 W. For the 16 nm technology, we demonstrate the importance of maintaining high threshold voltage to keep leakage power density at the acceptable level.

A multi-domain piezoresistive pressure sensor design tool based on analytical models

In recent years the MEMS market has grown rapidly. In parallel, design methodologies have developed in order to fulfil increasing design requirements. A finite-element- method analysis plays a key role in todays designer work. Even though, in case of some multi-domain systems such as micro pressure sensors, a FEM analysis is used at the beginning of the project, such an approach could be inefficient because even a simple multi-domain analysis could be very time consuming. Thus, in order to perform fast and reliable analysis which gives the designer an overview of sensors performance, an analytical model may be a solution. In this paper, a fast, dedicated tool for micromachined pressure sensor design based on analytical models is presented.

Impact of floorplanning and thermal vias placement on temperature in 2D and 3D processors

In modern integrated circuits, manufactured in nanometer technologies, reducing the hotspot temperature even by several degrees may lead to significant advantages. In particular, in high performance processors, lower temperature translates into fewer reliability concerns, lower cooling costs, the possibility of increasing the operating frequency and extending the devices lifetime. Therefore, in this paper we investigate how the positioning of particular processor units in the floorplan (i.e. floorplanning) affects the chip temperatures. We take into consideration 8-and 6-core processors manufactured in 14nm technology and simulate the temperature distribution for various floorplan designs. It is shown that the difference in maximal temperature for various floorplans can reach even 7.2K for a typical case. Moreover, the idea for thermal buffers is presented. While it is shown that thermal buffers may not be of great significance in 2D integrated circuits, obtained results indicate that in 3D ICs the combination of thermal buffers and vertical thermal vias may considerably reduce the temperature of the hottest areas.

A study on microbolometer electro-thermal circuit modelling

Electro-thermal models are commonly used in simulations and designing MEMS devices, also in case of microbolometers. These models allow to estimate sensors performance before fabrication that consequently impacts on fabrication cost. Coupling of electric and thermal domains and building appropriate model for carrying out simulations are crucial to detect all phenomena having impact for Readout Integrated Circuit. This article brings closer to the subject matter of circuit modelling (willingly implemented in MATLAB/SIMULINK or PSPICE tools) and to its theoretical background.

Test ASIC for investigation of thermal coupling in Many-Core Architectures

This paper presents the design of a test ASIC, which was intended for the investigation of thermal coupling in Many-Core Architectures. Particular sections of the paper describe in detail the design concept and simulated operation of the ASIC which is currently sent for manufacturing.

Analytical model of electrostatic membrane-Based actuators

In the design process, modelling is a fundamental stage which allows the designer to obtain a general overview of the device performance. Very often, this phase is very time-consuming, especially if a welloptimized device which fulfils very specific requirements is to be fabricated. Hence, a fast and reliable technique of simulation is needed and accurate tools have to be used to achieve this goal. In this paper, a simple method of electrostatic actuator modelling based on reduced analytical equations is presented and compared to commonly used FEM simulations. This method, despite some limitations, gives accurate results in much shorter time which might be crucial during the optimization phase.