Michal Szermer

Ion sensitive field effect transistor modelling for multidomain simulation purposes

Abstract The proper design and simulation of modern electronic microsystems oriented towards environment monitoring requires accurate models of various ambient sensors. In particular, this paper presents a comprehensive model of an ion sensitive field effect transistor (ISFET). The model can be employed straightforwardly for simulations at device, circuit or system level. First, the model was validated with electrical measurements and simulations of real structures performed for different ion concentration and temperature values. Then, the ISFET sensor model was employed for mixed-signal simulations in VHDL-AMS, when the analysis of a microsystem consisting of the ISFET sensor and a sigma–delta analogue-to-digital converter was carried out. Additionally, the presence of other ions than hydrogen in the measured solution was also taken into account in the simulations.

Dedicated thermal emulator for analysis of thermal coupling in many-core processors

Abstract This paper discusses the problem of thermal coupling in many-core processors manufactured in non-planar FinFET technologies. Our work focuses on two research goals. Firstly, the results obtained from the thermal simulations allow the investigation of mutual thermal influence between neighboring cores in such processors, what can be used to develop thermal models of such architectures. Secondly, we describe a test integrated circuit designed specifically to mimic the thermal behavior of microprocessors manufactured in various technologies. In particular, this paper describes its design and presents selected simulation results obtained using Green׳s function-based thermal software.

Evaluating the impact of scaling on temperature in FinFET-technology multicore processors

Every new technology node allows higher transistor density and more complex processors to be manufactured. Unfortunately, it also means that, for the same operating conditions, power density in the chip has to increase. However, it is not obvious how this increased power density translates into temperatures in the processor, therefore in this paper we analyze the influence of technology scaling on temperature of integrated circuit manufactured in FinFET technologies. The problem is discussed based on the results of both steady-state and transient thermal simulations obtained for two modern multi-core processors manufactured in 32nm and 22nm technologies.

Analysis of the effectiveness of core swapping in modern multicore processors

One of the interesting thermal management techniques for multi-core processors is core swapping. In this paper, using the published power data and floorplans for two modern high-performance processors, we employ the well-known HotSpot tool to perform the thermal simulation of the core swapping mechanism. Our transient simulations show that by using core swapping technique, it was possible to either minimize the hot spot temperature in the Ivy Bridge chip by 5°C or increase the operating frequency by 17% and maintain the same temperature as in the case without core swapping. We also derive an analytical model of the activity migration mechanism between two cores which may serve as a tool to calculate the swapping frequency given the desired maximal temperature drop. The model also allows for the correlation of the cooling effectiveness with the performance penalty induced by the swapping.

New methodology for thermal analysis of multi-core processors based on dedicated ASIC

Abstract Accurate prediction of thermal phenomena occurring in multi-core processors manufactured in new technologies prove to be both crucial and challenging. Therefore, in this paper, we introduce a new methodology for thermal analysis of such chips. The novelty of our approach is the use of a dedicated ASIC ( Application-Specific Integrated Circuit ), composed of a 16×24 array of heat cells, which emulates the power dissipation in a real processor and allows observing the chip temperature distribution in real-time. The ASIC takes as an input the power trace computed by the execution of benchmarks on a cycle-accurate processor simulator. The entire methodology flow is thoroughly described in the paper, including the details about the chip design and power modeling techniques. Post-layout simulations of our ASIC are used to verify the correctness of the design, whereas our approach to power modeling is validated using preliminary thermal simulations performed with existing software tools.

The evolution of MEMS and modelling methodologies

Purpose – The purpose of this paper is to show the evolution of microsystems together with modeling methods in the space of dozen years as a result of finished research in the frame of several projects.Design/methodology/approach – In this paper several approaches are presented. First, microsystems were built in multi project wafer technology. They were demonstrators like micromotor, micromirrors or micropumps modeled using dedicated design tool. A multi purpose chip was also designed using HDL description and FEM simulations. The next project concerned chemical sensors, where specialized models were developed and implemented in VHDL‐AMS in order to perform multidomain behavioral simulations. Dedicated tools were also developed for medical applications.Findings – The evolution of MEMS technology is strictly connected with simulation and modeling methods. The success and short time to market need fast and accurate simulation methods. This paper shows that the approach depends on application. Moreover, it i...

Cache leakage power estimation using architectural model for 32 nm and 16 nm technology nodes

The constant increase of subthreshold current of nanometer transistors due to technology scaling may hinder the evolution of high-performance chips in the near future. This evokes the need of accurate leakage power modeling for new nanometer technologies. In this paper, we present an improved subthreshold current model, which was integrated it into an architectural-level power simulator. Using this simulator, we estimated the leakage power in a 2 MB cache memory for 32 nm and 16 nm technology nodes. Our results show that the cache leakage power dissipation for 2 MB 2-way cache at 100°C fabricated in the 32 nm technology is around 1 W. For the 16 nm technology, we demonstrate the importance of maintaining high threshold voltage to keep leakage power density at the acceptable level.

Real time temperature monitoring of ICs with boundary temperature scan

This paper discusses the possibility of estimating in real time internal heat source temperature values based on the sensor measurements available only at circuit boundaries. The chances and some fundamental limitations of such a boundary temperature scan approach are illustrated based on an example of a test ASIC. This circuit contains a matrix of heat sources which can be individually switched on/off at different power levels. The temperature is monitored by a matrix of sensors located around the circuit layout. The sensor measurements can be processed by on-board digital filters, which provide estimates of heat source temperatures. In particular, the paper focuses on determining the optimal sensor locations, readout time instants and estimation algorithm parameters.

Mixed signal ASIC controller for satellite medium power DC/DC converters

The objective of this paper it to present a work concerning a proposed design and development of an analog Pulse Width Modulation (PWM) Application Specific Integrated Circuit (ASIC) with built-in analogue control loop and PWM for DC/DC power converters used in space applications. The described circuit can be used in avionics, aerospace devices and vehicles. The paper presents the general requirements that are needed for such component and shows its advantages over traditional. Finally, the paper discusses the way of the ASIC implementation, elaborated ASIC architecture and introductory works on its components. Means and ways of reaching space grade level are also presented.

A study on microbolometer electro-thermal circuit modelling

Electro-thermal models are commonly used in simulations and designing MEMS devices, also in case of microbolometers. These models allow to estimate sensors performance before fabrication that consequently impacts on fabrication cost. Coupling of electric and thermal domains and building appropriate model for carrying out simulations are crucial to detect all phenomena having impact for Readout Integrated Circuit. This article brings closer to the subject matter of circuit modelling (willingly implemented in MATLAB/SIMULINK or PSPICE tools) and to its theoretical background.