Piotr Zajac

Chip Self-Organization and Fault Tolerance in Massively Defective Multicore Arrays

We study chip self-organization and fault tolerance at the architectural level to improve dependable continuous operation of multicore arrays in massively defective nanotechnologies. Architectural self-organization results from the conjunction of self-diagnosis and self-disconnection mechanisms (to identify and isolate most permanently faulty or inaccessible cores and routers), plus self-discovery of routes to maintain the communication in the array. In the methodology presented in this work, chip self-diagnosis is performed in three steps, following an ascending order of complexity: interconnects are tested first, then routers through mutual test, and cores in the last step. The mutual testing of routers is especially important as faulty routers are disconnected by good ones with no assumption on the behavior of defective elements. Moreover, the disconnection of faulty routers is not physical (“hard”) but logical (“soft”) in that a good router simply stops communicating with any adjacent router diagnosed as defective. There is no physical reconfiguration in the chip and no need for spare elements. Ultimately, the multicore array may be viewed as a black box, which incorporates protection mechanisms and self-organizes, while the external control reduces to a simple chip validation test which, in the simplest cases, reduces to counting the number of valid and accessible cores.

Production Yield and Self-Configuration in the Future Massively Defective Nanochips

We address two problems in this work, namely, 1) the resilience challenge in the future chips made up of massively defective nanoelements and organized in replicative multicore architectures and 2) the issue of preserving the production yield. Our main suggestion is that the chip should be self-configuring at the architectural level, enabling with almost no external control mechanisms, core mutual-test to isolate the defective core and self-configuration of communications to discover the routes in the defective network. Our contribution is a systematic study of the dependence of the production yield versus the core failure probability (possibly as high as 0.4) in several networks with different node connectivity ranging from 3 to 5. The result is obtained in terms of a probabilistic metrics to warrant that a minimal fraction of nodes can be contacted by the input-output port for participating to the processing.

Self-Configuration and Reachability Metrics in Massively Defective Multiport Chips

The downsizing of transistor dimensions enabled in the future nanotechnologies will inevitably increase the number of faults in the complex ULSI chips. To maintain the production yield at acceptable level, several levels of protection mechanisms will have to be implemented to tolerate the permanent and transient faults occurring in the physical layers. In this paper, we study fault tolerance at the architectural level in multiport processor grids (MPG) through core dual diagnosis and self-configuration of communications. MPGs are considered to ensure the scalability of future hundred-core chips. We characterize defective technologies by the IOP reachability (i.e., the ability of the IOPs to contact a fraction of cores in the grid) that we study as a function of the fraction of defective cores or links. We show that almost all valid cores in the grid are accessible by all input-output ports (IOP) up to approximately 20-25% of defective cores. This property is quasi-independent of the position of the IOPs in the grid.

Dedicated thermal emulator for analysis of thermal coupling in many-core processors

Abstract This paper discusses the problem of thermal coupling in many-core processors manufactured in non-planar FinFET technologies. Our work focuses on two research goals. Firstly, the results obtained from the thermal simulations allow the investigation of mutual thermal influence between neighboring cores in such processors, what can be used to develop thermal models of such architectures. Secondly, we describe a test integrated circuit designed specifically to mimic the thermal behavior of microprocessors manufactured in various technologies. In particular, this paper describes its design and presents selected simulation results obtained using Green׳s function-based thermal software.

Evaluating the impact of scaling on temperature in FinFET-technology multicore processors

Every new technology node allows higher transistor density and more complex processors to be manufactured. Unfortunately, it also means that, for the same operating conditions, power density in the chip has to increase. However, it is not obvious how this increased power density translates into temperatures in the processor, therefore in this paper we analyze the influence of technology scaling on temperature of integrated circuit manufactured in FinFET technologies. The problem is discussed based on the results of both steady-state and transient thermal simulations obtained for two modern multi-core processors manufactured in 32nm and 22nm technologies.

Analysis of the effectiveness of core swapping in modern multicore processors

One of the interesting thermal management techniques for multi-core processors is core swapping. In this paper, using the published power data and floorplans for two modern high-performance processors, we employ the well-known HotSpot tool to perform the thermal simulation of the core swapping mechanism. Our transient simulations show that by using core swapping technique, it was possible to either minimize the hot spot temperature in the Ivy Bridge chip by 5°C or increase the operating frequency by 17% and maintain the same temperature as in the case without core swapping. We also derive an analytical model of the activity migration mechanism between two cores which may serve as a tool to calculate the swapping frequency given the desired maximal temperature drop. The model also allows for the correlation of the cooling effectiveness with the performance penalty induced by the swapping.

New methodology for thermal analysis of multi-core processors based on dedicated ASIC

Abstract Accurate prediction of thermal phenomena occurring in multi-core processors manufactured in new technologies prove to be both crucial and challenging. Therefore, in this paper, we introduce a new methodology for thermal analysis of such chips. The novelty of our approach is the use of a dedicated ASIC ( Application-Specific Integrated Circuit ), composed of a 16×24 array of heat cells, which emulates the power dissipation in a real processor and allows observing the chip temperature distribution in real-time. The ASIC takes as an input the power trace computed by the execution of benchmarks on a cycle-accurate processor simulator. The entire methodology flow is thoroughly described in the paper, including the details about the chip design and power modeling techniques. Post-layout simulations of our ASIC are used to verify the correctness of the design, whereas our approach to power modeling is validated using preliminary thermal simulations performed with existing software tools.

Enhanced self-configurability and yield in multicore grids

As we move deeper in the nanotechnology era, computer architecture is solicited to manipulate tremendous numbers of devices per chip with high defect densities. These trends provide new computing opportunities but efficiently exploiting them will require a shift towards novel, highly parallel architectures. Fault tolerant mechanisms will have to be integrated to the design to deal with the low yield of future nanofabrication processes. In this paper we consider multi processor grid (MPG) architectures that assure scalability beyond hundreds of cores per chip. We study self-diagnosis and self-configuration methods at the architectural level and propose an enhanced self-configuration methodology that enables usage of a maximum percentage of available fault-free cores in MPGs with high defect densities. We show that our approach achieves usability of all fault-free cores for the case of fault-free routers whereas previous work was efficient for defect densities of up to 20–25% of defective cores. We also address the case of faulty routers, achieving usability of almost all fault-free nodes (fault-free cores having a fault-free router) for very high defect densities both in the cores and in the routers.

Coupled thermo-fluidic simulation for design space exploration of microchannels in liquid-cooled 3D ICs

Integrated liquid cooling is a promising idea for future 3D integrated circuits and potentially a scalable solution for ever-increasing power dissipation. In this paper, we analyze the efficiency of heat removal from a 3D stacked chip with microchannels. We build a detailed chip model and perform a coupled thermo-fluidic finite element method simulation for various microchannel designs. We explore the design space and point out the correlations between various chip and cooling parameters. In particular, we show that with ten microchannels of size 500 μm × 70 μm it is possible to remove 100 W of heat from a two-tier 3D chip while maintaining the temperature below 90°C and the pressure drop below 50 kPa.

Cache leakage power estimation using architectural model for 32 nm and 16 nm technology nodes

The constant increase of subthreshold current of nanometer transistors due to technology scaling may hinder the evolution of high-performance chips in the near future. This evokes the need of accurate leakage power modeling for new nanometer technologies. In this paper, we present an improved subthreshold current model, which was integrated it into an architectural-level power simulator. Using this simulator, we estimated the leakage power in a 2 MB cache memory for 32 nm and 16 nm technology nodes. Our results show that the cache leakage power dissipation for 2 MB 2-way cache at 100°C fabricated in the 32 nm technology is around 1 W. For the 16 nm technology, we demonstrate the importance of maintaining high threshold voltage to keep leakage power density at the acceptable level.