Chae-Hag Yi

Real-time adjustment of power management policy for a time-based power control architecture

As state-of-the-art mobile devices are demanded for high performance and attractive designs, system-on-chips have been integrated with many functional blocks into a single chip to reduce the chip size, cost, and power consumption. In this paper, to reduce power consumption of heterogeneous processor, a power management algorithm is proposed with a time-based power control architecture which autonomously performs voltage/clock scaling operations without the intervention of the processors. The proposed algorithm has adaptively adjusted time-threshold levels for voltage/clock control to minimize the power consumption and work in severe time-constraints for real-time processing. The real-time adjustment makes robust performance of the power consumption guarantee regardless of patterns of data traffic and diverse application programs. To show performance of the proposed, they are adopted to an application processor integrated with a communication processor for smartphones. Via electronic system-level simulation, it is shown that the proposed algorithm reduces the power consumption by approximately 40%.

High-performance low-power application processor integrated with modem processor

An architecture is proposed to design a single chip with an application processor (AP) and a modem processor (MP). As an aggressive challenge, the MPs dedicated memory is removed to share the main memory with the AP. In addition, an autonomous power management (APM) is presented to reduce the power consumption of time-constrained tasks such as wireless communication. The APM is designed without the intervention of the microprocessors, to deal with the random and sparse data pattern of voice communication. For the architectural exploration, an electronic system-level simulation is performed for verifying the performance and power consumption. Through the simulation results, the proposed architecture exhibits small size, good performance and energy consumption.

Linear Secrecy Capacity Scaling in Dense Networks

We propose a new hierarchical cooperation technique using jamming in dense networks to achieve linear secrecy capacity scaling. To show the effect of the jamming signal in the proposed scheme, we derive the tolerable intensities of eavesdroppers to achieve the linear secrecy capacity scaling for hierarchical cooperation schemes with and without jamming, respectively. Although both hierarchical cooperation schemes can achieve the linear secrecy capacity scaling, only the proposed hierarchical cooperation scheme using jamming can achieve meaningful tolerable intensity of eavesdroppers.

An adaptive Log-likelihood Ratio compression algorithm for Downlink Shared Channel processing in LTE receiver

In high data rate communication systems using a Hybrid Automatic Repeat Request, Log-likelihood Ratio (LLR) values should be handled effectively and optimally for reducing memory size. In the paper an adaptive compression algorithm for LLR values is proposed. The approach is based on a dynamic two-dimensional quantization principle and a Huffman encoding. The algorithm was verified for QPSK, 16QAM and 64QAM modulations. Simulation results show a relatively low performance degradation (within 0.5 dB at low SNR range) when a constraint of 2.4 bits per LLR is applied.

New two-hop multiple relay protocol with H-ARQ in the absence of a direct link

In this paper, we devise and comprehensively analyze an efficient transmission protocol for multiple half-duplex relay communication without a direct link but with inter-relay interference. The proposed protocol achieves high diversity gain with the help of Hybrid Automatic Retransmission reQuest (H-ARQ) even when multiplexing gain is quite high. As the maximum allowable number of retransmission rounds (L) increases, an additional time diversity gain is obtained in short-term static channels. Compared to pre-existing protocols which adopt H-ARQ in a similar manner, its diversity gain at high multiplexing gain is much improved. As L increases, the dominating region become wider. In addition, in long-term static channels, we show that more than two retransmissions (i.e., L > 2) are unnecessary for improvement of the diversity gain.

Propagation delay detection based on I-Q modulation for indoor positioning system

An indoor positioning system has become a hot issue to provide a location-based service such as direction tracking, geofencing and private tracking. This paper addresses a phase-detection algorithm based on the Wi-Fi for proximity estimation between a transmitter and a receiver. In addition, the mathematical analysis of the phase-detection is shown based on the I-Q modulation. The algorithm has been designed with a combination of round-trip time measurement and quadrature modulation technique, that can have a positioning accuracy of 1m. Moreover, the quadrature modulation utilizes low frequencies, so the power consumption can be reduced. The accurate performance of the proposed estimation was verified by means of simulation results.

Low complexity, real-time adjusted power management policy using Golden Section Search

Golden Section Search (GSS) is applied to optimize the time threshold in a time-out power management policy. To reduce power consumption, modern system on chips selectively turns off some of its idling parts. If an idling block is kept awake for too long, it is wasting power; if it fails to predict a request, it will reduce the system performance due to wake-up time. The request of each part depends on external random events. This problem is usually addressed with a time-out policy, where the time-out value must be optimized in real time to cope with the system usage characteristics. Without the aid of prior knowledge, the GSS driven power policy consumed 15% more power than the absolute lower bound and 7% more power than the best fixed time threshold with a priori knowledge. The proposed method was evaluated with interrupt data of a 2G modem, captured from a real device in use.

A low power GPS/Galileo/GLONASS receiver in 65nm CMOS

A low power GPS/Galileo/GLONASS receiver is presented. The single chip supports GPS/Galileo and GLONASS operation simultaneously. To operate both application simultaneously, two mixers and two baseband filters are used. The chip size is 3.24 mm2 including bonding PAD. The system noise figure (NF) is 1.95 dB including SAW filter which loss is 1 dB. Power consumption is 23.6 mW for GPS/Galileo operation and 25.4 mW for GLONASS operation from 1.2V supply.

Reed-Solomon coding scheme for dual diversity systems with M-ary orthogonal signalling in Rayleigh fading channels

Diversity systems are used for reliable communication in fading channels. Two Reed-Solomon (RS) coding schemes are considered for dual diversity systems with M-ary orthogonal signalling in Rayleigh fading channels. We examine the after-decoding property of RS codes with bounded distance decoding and show that the second scheme utilizes the inherent error detecting capability of low rate RS codes. The RS (n, k/2) codes with symbol diversity order 1 significantly reduce the probability of undetected word error among accepted codewords and give comparable throughput to that of RS (n, k) codes with symbol diversity order 2.