Soo-Yong Kim

Modified Two-Dimensional Soft Output Viterbi Algorithm with Two-Dimensional Partial Response Target for Holographic Data Storage

The previously modified two-dimensional (2D) soft output Viterbi algorithm (SOVA) for holographic data storage (HDS) consists of four one-dimensional (1D) SOVAs in accordance with two different 1D partial response (PR) targets (vertical and horizontal directions). In this study, we propose a detection method in structural accordance with a 2D PR target through the use of the modified 2D SOVA. The proposed method shows superior bit error rate performance owing to the use of a 2D PR target that contains more information than the 1D PR target. Moreover, a reduction in power consumption, computational complexity, and the system-on-chip size for HDS system can be expected as a result of the use of only one 2D equalizer.

Real-time adjustment of power management policy for a time-based power control architecture

As state-of-the-art mobile devices are demanded for high performance and attractive designs, system-on-chips have been integrated with many functional blocks into a single chip to reduce the chip size, cost, and power consumption. In this paper, to reduce power consumption of heterogeneous processor, a power management algorithm is proposed with a time-based power control architecture which autonomously performs voltage/clock scaling operations without the intervention of the processors. The proposed algorithm has adaptively adjusted time-threshold levels for voltage/clock control to minimize the power consumption and work in severe time-constraints for real-time processing. The real-time adjustment makes robust performance of the power consumption guarantee regardless of patterns of data traffic and diverse application programs. To show performance of the proposed, they are adopted to an application processor integrated with a communication processor for smartphones. Via electronic system-level simulation, it is shown that the proposed algorithm reduces the power consumption by approximately 40%.

Two-Dimensional Soft Output Viterbi Algorithm with a Variable Reliability Factor for Holographic Data Storage

In a practical holographic data storage system, the reconstruction process for a data page should account for the processing time as well as the bit error rate (BER) performance. To improve both aspects, we introduce two-dimensional (2D) partial response maximum likelihood composed of a 2D partial response (PR) target including diagonal elements and a 2D soft output Viterbi algorithm (SOVA) with a variable reliability factor. The 2D SOVA performs two one-dimensional (1D) SOVAs in structural accordance with the 2D PR target where extrinsic information uses the expected value calculated on a synchronization pattern. Finally, the 2D SOVA exports a weighted average using the reliability factor that is updated similarly as the optimization scheme for each page. The simulation results show that the proposed method has superior BER performance, despite using only two 1D SOVAs as compared with the modified 2D SOVA composed of four 1D SOVAs.

High-performance low-power application processor integrated with modem processor

An architecture is proposed to design a single chip with an application processor (AP) and a modem processor (MP). As an aggressive challenge, the MPs dedicated memory is removed to share the main memory with the AP. In addition, an autonomous power management (APM) is presented to reduce the power consumption of time-constrained tasks such as wireless communication. The APM is designed without the intervention of the microprocessors, to deal with the random and sparse data pattern of voice communication. For the architectural exploration, an electronic system-level simulation is performed for verifying the performance and power consumption. Through the simulation results, the proposed architecture exhibits small size, good performance and energy consumption.

System Identification Using Embedded Dynamic Signal Analyzer

The effect of model uncertainty is increased in optical disc drives (ODDs) because the mechanical and electrical components are manufactured with a wide error tolerance to reduce production costs. In this paper, we introduce a new technique for system identification whereby an embedded dynamic signal analyzer (EDSA) is used for the estimation of the system frequency characteristics. The estimated transfer function can be utilized to adapt a controller and improve the performance and stability of the system in terms of the model uncertainty. The EDSA comprises a sine generator, system identifier, and band-pass filter. A design methodology is proposed for the production of an accurate and cost-effective sine signal, which minimizes error and prevents overflow. Moreover, the proposed algorithms are implemented in a system-on-chip for an ODD. The experimental results show that the EDSA exhibits good performance and reliability.

A parallel collaborative sphere decoder for a MIMO communication system

In this paper, we propose a parallel collaborative sphere decoder with a scalable architecture promising quasi-maximum likelyhood performance with a relatively small amount of computational resources. This design offers a hardware-friendly algorithm using a modified node operation through fixing the variable complexity of the critical path caused by the sequential nature of the conventional sphere decoder (SD). It also reduces the computational complexity compared to the fixed-complexity sphere decoder (FSD) algorithm by tree pruning using collaboratively operated node operators. A Monte Carlo simulation shows that our proposed design can be implemented using only half the parallel operators compared to the approach using an ideal fully parallel scheme such as FSD, with only about a 7% increase of the normalized decoding time for MIMO dimensions of 16×16 with 16-QAM modulation.

Propagation delay detection based on I-Q modulation for indoor positioning system

An indoor positioning system has become a hot issue to provide a location-based service such as direction tracking, geofencing and private tracking. This paper addresses a phase-detection algorithm based on the Wi-Fi for proximity estimation between a transmitter and a receiver. In addition, the mathematical analysis of the phase-detection is shown based on the I-Q modulation. The algorithm has been designed with a combination of round-trip time measurement and quadrature modulation technique, that can have a positioning accuracy of 1m. Moreover, the quadrature modulation utilizes low frequencies, so the power consumption can be reduced. The accurate performance of the proposed estimation was verified by means of simulation results.

Low-power shared memory architecture power mode for mobile system-on-chip

This paper presents dynamic power saving schemes for low power operation in the modem system shared memory architecture of mobile system-on-a-chip (SOC). Different power modes are considered to obtain the minimum power consumption in a modem operation. An electronic system level (ESL) virtual platform is implemented to verify the proposed scheme with real traffic data extracted from the actual phone. Experimental results show that the proposed method reduces the power consumption by 42% and 15% in 2G and 3G respectively.

Low complexity, real-time adjusted power management policy using Golden Section Search

Golden Section Search (GSS) is applied to optimize the time threshold in a time-out power management policy. To reduce power consumption, modern system on chips selectively turns off some of its idling parts. If an idling block is kept awake for too long, it is wasting power; if it fails to predict a request, it will reduce the system performance due to wake-up time. The request of each part depends on external random events. This problem is usually addressed with a time-out policy, where the time-out value must be optimized in real time to cope with the system usage characteristics. Without the aid of prior knowledge, the GSS driven power policy consumed 15% more power than the absolute lower bound and 7% more power than the best fixed time threshold with a priori knowledge. The proposed method was evaluated with interrupt data of a 2G modem, captured from a real device in use.