Chan Hua Vun

A New RNS based DA Approach for Inner Product Computation

This paper presents a novel method to perform inner product computation based on the distributed arithmetic principles. The input data are represented in the residue domain and are encoded using the thermometer code format while the output data are encoded in the one-hot code format. Compared to the conventional distributed arithmetic based system using binary coded format to represent the residues, the proposed system using the thermometer code encoded residues provides a simple means to perform the modular inner products computation due to the absence of the 2 modulo operation encountered in conventional binary code encoded system. In addition, the modulo adder used in the proposed system can be implemented using simple shifter based circuit utilizing one-hot code format. As there is no carry propagation involved in the addition using one-hot code, while the modulo operation can be performed automatically during the addition process, the operating speed of the one-hot code based modulo adder is much superior compared to the conventional binary code based modulo adder. As inner product is used extensively in FIR filter design, SPICE simulation results for an FIR filter implemented using the proposed system is also presented to demonstrate the validity of the proposed scheme.

RNS encoding based folding ADC

This paper presents a novel encoding scheme based on the residue number systems for folding ADC to enable highly efficient hardware implementation of high speed, high resolution ADC. The input analog signal is folded by multiple groups of zero-crossing based folding circuits of different folding factors corresponding to the moduli used for their implementation. Each group of folding circuits in turn contains multiple parallel zero-crossing based folding circuits of same folding factor, but with their outputs phase shifted with respect to one another such that their collective output bits pattern form a residue of the modulus of the group. Multiple groups of folding circuits with different moduli that are relatively prime to each other are then combined in parallel. When taken together, their digital outputs form residue digits of a relatively prime moduli set that allows unique representation of the input signal magnitude over a dynamic range that is equal to the product of the moduli used in the different groups in the ADC.

A low-power pipelined MAC architecture using Baugh-Wooley based multiplier

Multiply-accumulator (MAC) is the central unit used in digital signal processors (DSP) that are now widely found in many consumer electronic devices. With current emphasis on minimizing operating power and yet maximizing computation performance for DSPs, efficient MAC architecture with low power consumption and high computation performance is hence desired. This paper proposes a low power pipelined MAC architecture that incorporates a 16×16 multiplier using Baugh-Wooley algorithm with high performance multiplier tree, together with clock gating the idle pipeline stages to reduce the power consumption. Our simulations show that the power consumption of the proposed architecture is 30% to 80% less than the other contemporary MAC architectures, without compromising its computation performance.

Thermometer Code Based Modular Arithmetic

This paper presents a novel approach to perform modular arithmetic addition and subtraction using base-1 thermometer code data format for operands corresponding to the residues of the same modulus. Two n-bit thermometer code operands are first concatenated and logically shifted to produce a normalized 2n-bit thermometer code intermediate sum. Modulo operation is then applied to this 2n-bit intermediate sum to produce an n-bit datum corresponding to the modular sum of the two input operands. This approach greatly simplifies the modulo addition operation by eliminating the carry bit propagation during the arithmetic operation encountered when using the conventional base-2 binary code data format. It also enables practical applications of modular arithmetic for signal processing algorithms in a very efficient way. Circuit for implementing the modular arithmetic units using multiplexers and basic logic gates are also described in this paper.

An efficient compressive spectrum sensing technique for cognitive radio system

This paper presents a compressive sampling technique incorporated with feature learning to achieve highly effective and flexible spectrum sensing for hybrid cognitive radio operation using the combination of underlay and interweave transmission modes. Leading eigenvectors are first extracted from compressively sampled training sets of primary signals, whose learned features are then used for signal detection based on the general likelihood ratio test. Compared to existing approaches that are typically non-blind and operate at Nyquist sampling rate, simulation results based on IEEE 802.22 WRAN environment show that the proposed technique is able to achieve higher transmission throughput, while operating at 17% of Nyquist sampling rate performed over a shorter spectrum sensing duration.

Algorithm for 3D orientation estimation based on Kalman Filter and Gradient Descent

Individual wearable device orientation plays a crucial role in rehabilitation application, especially in the process of monitoring dynamic changes of movement for clinical prognosis. This paper proposed a combined approach to fuse Inertial Measurement Unit (IMU) sensors via adaptive Kalman Filter considering practical recommendation of error covariance. Our approach associates orientation estimate using gyroscope via Kalman Filter with optimal instant attitude estimate of accelerometer and magnetometer using Gradient Descent. Experiments were carried out to compare our proposed approach with well-known approaches such as Kalman filter, Tilt Kalman filter, and Madgwick algorithm. The results show that the proposed method displayed accurate and precise measurements, especially for internal/external rotation (z axis orientation), in real time.

A Novel Matrix Optimization for Compressive Sampling-Based Sub-Nyquist OFDM Receiver in Cognitive Radio

Modulated wideband converter is the most commonly accepted technique for implementing sub-Nyquist compressive sampling-based wireless receiver to reduce the analog and digital processing complexity when detecting wideband spectrum for cognitive radio systems. However, the issue of non-optimal mutual coherence, which leads to a higher receiving bit error rate, has not been considered in existing compressive sampling-based cognitive radio studies. Furthermore, existing theoretical compressive sampling-based solutions cannot be directly applied because typical modulated wideband converter-based designs use fixed parameters that cannot be easily updated during their sampling operations. This paper presents a novel matrix optimization which can be incorporated into modulated wideband converter-based cognitive radio to enhance its detection accuracy for OFDM signals. The proposed approach can also be predetermined to reduce the computation complexity, while remains compatible with standard digital OFDM receiver’s operation. Simulation results show that our proposed system can consistently produce smaller compressive sampling reconstruction error in terms of lower bit error rate under various operating conditions compared to existing systems.

A Feature-Based Compressive Spectrum Sensing Technique for Cognitive Radio Operation

In cognitive radio systems, data throughput of the secondary user is an important performance metric used to evaluate the spectrum usage efficiency. As such, the effectiveness of the spectrum sensing process used by the secondary user, namely the spectrum sensing accuracy, its sampling time and processing time will have significant impacts on the data throughput performance. This paper presents a novel wideband spectrum sensing technique operating at low sub-Nyquist sampling rate that can achieve high sensing accuracy and high throughput without high computational cost. The proposed technique applies a novel likelihood ratio test on the learned feature information of the primary signal for efficient spectrum sensing, which is based directly on the compressive data collected by a sub-Nyquist sampler. Comprehensive analysis of the sensing-throughput performance for various commonly used spectrum sensing techniques is also presented, which are then used to compare against the proposed technique. Simulation results using real-world ATSC DTV data operating in IEEE 802.22 WRAN environment show that due to the higher detection accuracy and shorter spectrum sensing duration, the proposed technique is able to achieve better achievable secondary user’s transmission throughput compared to other well-known spectrum sensing techniques, while operating at 0.17 time of the Nyquist sampling rate.

Fracturable DSP Block for Multi-context Reconfigurable Architectures

Multi-context architectures like NATURE enable low-power applications to leverage fast context switching for improved energy efficiency and lower area footprint. The NATURE architecture incorporates 16-bit reconfigurable DSP blocks for accelerating arithmetic computations; however, their fixed precision prevents efficient reuse in mixed-width arithmetic circuits. This paper presents an improved DSP block architecture for NATURE, with native support for temporal folding and run-time fracturability. The proposed DSP block can compute multiple sub-width operations in the same clock cycle and can dynamically switch between sub-width and full-width operations in different cycles. The NanoMap tool for mapping circuits onto NATURE is extended to exploit the fracturable multiplier unit incorporated in the DSP block. We demonstrate the efficiency of the proposed dynamically fracturable DSP block by implementing logic-intensive and compute-intensive benchmark applications. Our results illustrate that the fracturable DSP block can achieve a 53.7% reduction in DSP block utilization and a 42.5% reduction in area with a 122.5% reduction in power–delay product (P–D) without exploiting logic folding. We also observe an average reduction of 6.43% in P–D for circuits that utilize NATURE’s temporal folding compared to the existing full precision DSP block in NATURE, leading to highly compact, energy efficient designs.

Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures

Dynamically reconfigurable architectures, such as NATURE, achieve high logic density and low reconfiguration latency compared to traditional field-programmable gate arrays. Unlike fine-grained NATURE, reconfigurable DSP block incorporated NATURE architecture achieves significant improvement in performance for mapping compute-intensive arithmetic operations. However, the DSP block fails to fully exploit the potential provided by the run-time reconfiguration. This paper presents a pipeline reconfigurable DSP architecture to target the NATURE platform that supports temporal logic folding. The proposed approach allows the DSP pipeline stages to be reconfigured independently such that different functions can be performed distinctively and individually at every clock interval during runtime. In addition, a multistage clock gating technique is also used in the design to minimize the power consumption. We also extend NanoMap tool for mapping circuits on NATURE platform to exploit the pipeline-level reconfigurability of our proposed DSP block to enable efficient resource sharing and area/power reduction. Simulation results on 13 benchmarks show that the proposed approach enables area-delay improvement of up to 3.6