Chan-Kwang Park

1 Giga bit SOI DRAM with fully bulk compatible process and body-contacted SOI MOSFET structure

1 Gbit SOI DRAM with a body-contacted (BC) SOI MOSFET structure is successfully realized for the first time. The fabricated 1G SOI DRAM has fully compatible process with 0.17 /spl mu/m bulk CMOS technology except for the isolation process. The key advantage of BC-SOI MOSFET is freedom from the floating-body effect, since the body-potential increase can be suppressed by the well contact through the remaining thin-silicon film beneath the field oxide. The BC-SOI structure has several advantages, such as relatively high isolation punchthrough voltage, high drain-to-source breakdown voltage compared with conventional thin-film SOI MOSFETs and small junction capacitance compared with bulk MOSFETs, resulting in high-speed circuit operation.

Offset-trimming bit-line sensing scheme for gigabit-scale DRAM's

A new offset-trimming bit-line sensing scheme is described which is suitable for Gigabit-scale DRAMs. This sensing scheme can suppress the sensitivity degradation caused by the large electrical parameter variation of deep submicron transistors. The effective offset voltage dependence on trimming time is analyzed and verified with simulation results. As compared with a conventional direct sensing scheme, the proposed scheme shows remarkable improvement on the sensitivity. A test device was fabricated with a 0.25 ¿m CMOS technology and its measurement results indicate the successful operation of offset-trimming.