Chan-Soo Hwang

Beyond 3G: vision, requirements, and enabling technologies

This article introduces the vision and requirements for future development of mobile communications systems, and discusses several key enabling technologies such as modulation and multiple access schemes, multiple antenna techniques, and an IP-based network, considered important to realize this vision in real-world systems.

MetaCore: an application specific DSP development system

This paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time. MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and a formal specification of ISA (Instruction Set Architecture), and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration is chosen, the system helps generate a VLSI processor design in the form of HDL along with the application program development tools such as C compiler, assembler and instruction set simulator.

MetaCore: an application-specific programmable DSP development system

This paper describes the MetaCore system which is an application-specific instruction-set processor (ASIP) development system targeted for digital signal processor (DSP) applications. The goal of the MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost, and design turnaround time. The MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and structural/behavioral specifications for the target processor and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration and instruction set are chosen, the system helps generate the target processor design in the form of hardware description language (HDL) along with the application program development tools such as C compiler, assembler, and instruction set simulator. The effectiveness of the MetaCore system was verified with a successful design of MDSP-II, a programmable DSP processor targeted for mobile communication.

MDSP-II: a 16-bit DSP with mobile communication accelerator

This paper describes a 16-bit programmable fixed-point digital signal processor, called MDSP-II, for mobile communication applications. The instruction set of MDSP-II was determined after a careful analysis of the Global System for Mobile communications (GSM) baseband functions. An application-specific hardware block called the mobile communication accelerator (MCA) was incorporated on chip to accelerate the execution of the key operations frequently appearing in Viterbi equalization. With the assistance of MCA, the GSM baseband functions, which need 53 million instructions per second (MIPS) on the general-purpose digital signal processors, can be performed only with 19 MIPS. The MDSP-II was implemented with a 0.6-/spl mu/m triple-layer metal CMOS process on a 9.7/spl times/9.8 mm/sup 2/ silicon area and was operated up to 50 MHz clock frequency.

A Full-Diversity Full-Rate Space-Time Block Code Design for Three Transmit Antennas

A design of non-orthogonal 3 × 3 space-time block code (STBC) is proposed. The proposed design achieves full rate, full level diversity, and maximum coding gain by symbol rotation (SR) method. In addition, the proposed scheme has lower encoding complexity than the unitary constellation-rotation (CR) STBC, while two methods exhibit the same.

High Rate Space Time Block Codes

High Rate Space-Time Block Codes (HR-STBCs) with greater than 1 symbol/transmission and simple decoding schemes are proposed. The HR-STBC demonstrates 3 dB E b /N 0 gain at BER = 10 -3 compared with the conventional STBC when three transmit antennas and two receive antennas are utilized.

Differential Space Time Block Codes Using Nonconstant Modulus Constellations for Four Transmit Antennas

We extend the differential space time block code (STBC) using nonconstant modulus constellations of two transmit antennas to four transmit antennas case. The proposed method obtains larger minimum Euclidean distances than those of conventional differential STBC with PSK constellations. We derive the symbol error rate (SER) performance of the proposed method and demonstrate the SER performance using computer simulations for both static and fast fading channels. For transmission rates greater than 2 bits/channel use and 3 bits/channel use, the proposed method outperforms the conventional differential STBC.

Differential Detection of Multiple Antenna Systems with High Transmission Rate

A differential detection Space-Time Block Code (STBC) is proposed with a high transmission rate, allowing a trade-off between diversity and multiplexing gain with low encoding and decoding complexity. The proposed method offers multiplexing gain by doubling the transmission rate for three and four transmission antennas. Computer simulations demonstrate that the proposed STBC can achieve a 5.8dB E b /N 0 gain at BER = 10 -3 compared with a conventional differential detection STBC for four transmission and two receiving antennas.