Chong-Min Kyung

A Lossless Embedded Compression Using Significant Bit Truncation for HD Video Coding

Increasing the image size of a video sequence aggravates the memory bandwidth problem of a video coding system. Despite many embedded compression (EC) algorithms proposed to overcome this problem, no lossless EC algorithm able to handle high-definition (HD) size video sequences has been proposed thus far. In this paper, a lossless EC algorithm for HD video sequences and related hardware architecture is proposed. The proposed algorithm consists of two steps. The first is a hierarchical prediction method based on pixel averaging and copying. The second step involves significant bit truncation (SBT) which encodes prediction errors in a group with the same number of bits so that the multiple prediction errors are decoded in a clock cycle. The theoretical lower bound of the compression ratio of the SBT coding was also derived. Experimental results have shown a 60% reduction of memory bandwidth on average. Hardware implementation results have shown that a throughput of 14.2 pixels/cycle can be achieved with 36 K gates, which is sufficient to handle HD-size video sequences in real time.

Fast development of source-level debugging system using hardware emulation

We describe the co-development of a processor and its source-level debugging system using an emulation-based validation technology including hardware emulation, not simulation, Since a source-level debugging system is essential to develop an application system and it takes a long time to validate the functionality of the source-level debugging system, we have adopted hardware emulation for a fast validation and system development. Using this methodology, we were able to validate the source-level debugging system successfully before the chip fabrication.

A floorplan-based planning methodology for power and clock distribution in ASICs

In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution methodology for ASIC design. From the oorplan and the estimated power consumption, the power network size is determined at an early design stage. Next, without detailed gate-level netlist, clock interconnect sizing, the number and strength of clock bu ers are planned for balanced clock distribution. This early planning methodology at the full-chip level enables us to x the global interconnect issues before the detailed layout composition is started.

FAMOS: an efficient scheduling algorithm for high-level synthesis

FAMOS, an iterative improvement scheduling algorithm for the high-level synthesis of digital systems, is described. The algorithm is based on a move acceptance strategy and various selection functions defined to represent the cost of hardware resources such as functional units and registers. A main feature of the algorithm is that it can escape from local minima. The algorithm can deal with diverse design styles such as multi-cycle operations, chained operations, pipelined datapaths, pipelined functional units and conditional branches. Register costs and maximal time constraints are also considered. To efficiently represent information on the design styles, a graph model called weighted precedence graph is proposed as a general model on which the scheduling algorithm is based. Despite the iterative nature, the proposed algorithm has a polynomial time complexity. Although the optimality of the algorithm is not guaranteed, optimal solutions were obtained for several examples available from the literature. >

Fast and near optimal scheduling in automatic data path synthesis

A new heuristic scheduling alg.orithm which has a feature of escaping from local minima is presented. The algorithm has a polynomial time complexity in spite of its iterative nature. Although there is no guarantee for the optimality, the algorithm produced optimal results for the experimental examples of earlier works. A graph model which contains information on the real world constraints such as multi-cycle operations, chained operations and pipelined data paths is also proposed as a general model on which our scheduling algorithm is based.

Suppressing rolling-shutter distortion of CMOS image sensors by motion vector detection

This paper focuses on the rolling shutter distortion of CMOS image sensor coming from its unique readout mechanism as the main cause for image degradation when there are fast-moving objects. This paper proposes a post image processing scheme based on motion vector detection to suppress the rolling shutter distortion. Motion vector detection is performed based on an optical flow method at a reasonable computational complexity. A practical implementation scheme is also described.

A Multitransform Architecture for H.264/AVC High-Profile Coders

This paper presents a high-throughput, cost-effective implementation of six different integer transforms in the H.264/AVC high-profile coders, i.e., 4 × 4 forward, 4 × 4 inverse, forward Hadamard, inverse Hadamard, 8 × 8 forward, and 8 × 8 inverse transform, all integrated as a shared hardware. The 4 × 4 transform matrices are regularized by using permutation, partitioned into 2 × 2 blocks, and factored for maximal hardware sharing. By using two types of 4 × 4 transform matrices included in an 8 × 8 transform matrix, two different 8 × 8 transforms are both described as three steps and unified with minor modification. To improve throughput of the transform, two independent 4 × 4 transform blocks within the 8 × 8 transform block operate in parallel in the 4 × 4 transform mode, while the two-stage pipelined architecture is used in the 8 × 8 transform mode. Using 0.18-¿m CMOS technology, the maximum operating frequency of the proposed multitransform architecture is 200 MHz, which achieves 4.1 Gpixels/sec throughput rate with the hardware cost of 63618 gates. Compared with existing designs, the proposed design delivers at least 54% higher throughput at 38% higher throughput/area ratio in Adaptive Block-size Transform (ABT) mode.

Communication-efficient hardware acceleration for fast functional simulation

This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more time-consuming as design complexity increases. To accelerate functional simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. Hardware accelerated simulation dramatically reduces the simulation time. However, the communication overhead between the software simulator and hardware accelerator is becoming a new critical bottleneck. We reduce the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting testbench and moving a part of testbench into hardware accelerator. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to conventional hardware accelerated simulation while maintaining the cycle accuracy and compatibility with the original testbench.

Synthesis of application specific instructions for embedded DSP software

Application specific instructions play an important role in reducing the required code size and increasing performance. This paper describes a new approach to generate application specific instructions for DSP applications. The proposed approach is based on a modified subset-sum problem, and can support multi-cycle complex instructions as well as single cycle instructions, while the previous state-of-the-art approaches can generate only the single-cycle instructions or can just select instructions from the fixed super-set of possible instructions. In addition, the proposed approach can also be applicable to the case that instructions are predefined. The experimental results on real applications show that the proposed approach is effective in making the instructions meet the given constraints without attaching special hardware accelerators.

MetaCore: an application specific DSP development system

This paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time. MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and a formal specification of ISA (Instruction Set Architecture), and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration is chosen, the system helps generate a VLSI processor design in the form of HDL along with the application program development tools such as C compiler, assembler and instruction set simulator.