Byoung-Woon Kim

Fast development of source-level debugging system using hardware emulation

We describe the co-development of a processor and its source-level debugging system using an emulation-based validation technology including hardware emulation, not simulation, Since a source-level debugging system is essential to develop an application system and it takes a long time to validate the functionality of the source-level debugging system, we have adopted hardware emulation for a fast validation and system development. Using this methodology, we were able to validate the source-level debugging system successfully before the chip fabrication.

MetaCore: an application specific DSP development system

This paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time. MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and a formal specification of ISA (Instruction Set Architecture), and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration is chosen, the system helps generate a VLSI processor design in the form of HDL along with the application program development tools such as C compiler, assembler and instruction set simulator.

MetaCore: an application-specific programmable DSP development system

This paper describes the MetaCore system which is an application-specific instruction-set processor (ASIP) development system targeted for digital signal processor (DSP) applications. The goal of the MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost, and design turnaround time. The MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and structural/behavioral specifications for the target processor and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration and instruction set are chosen, the system helps generate the target processor design in the form of hardware description language (HDL) along with the application program development tools such as C compiler, assembler, and instruction set simulator. The effectiveness of the MetaCore system was verified with a successful design of MDSP-II, a programmable DSP processor targeted for mobile communication.

MDSP-II: a 16-bit DSP with mobile communication accelerator

This paper describes a 16-bit programmable fixed-point digital signal processor, called MDSP-II, for mobile communication applications. The instruction set of MDSP-II was determined after a careful analysis of the Global System for Mobile communications (GSM) baseband functions. An application-specific hardware block called the mobile communication accelerator (MCA) was incorporated on chip to accelerate the execution of the key operations frequently appearing in Viterbi equalization. With the assistance of MCA, the GSM baseband functions, which need 53 million instructions per second (MIPS) on the general-purpose digital signal processors, can be performed only with 19 MIPS. The MDSP-II was implemented with a 0.6-/spl mu/m triple-layer metal CMOS process on a 9.7/spl times/9.8 mm/sup 2/ silicon area and was operated up to 50 MHz clock frequency.

Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis

This paper presents an intellectual property (IP)-based system-on-chip (SoC) synthesis framework focusing on how to select IPs from different sources and how to integrate the selected IPs using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IPs with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is converted into an equivalent mixed integer linear programming (MILP) model without increasing the computational complexity. Then, the equivalent MILP model is solved to decide whether each IP is selected or not, and to locate the selected IP on the optimal on-chip bus of a hierarchical bus architecture that consists of on-chip buses with different bus attributes. Experimental results on an MP3 decoding system show that the IP-centric design space with uncertainty can be successfully explored using the proposed scheme.

MetaCore: a configurable & instruction-level extensible DSP core

The design of application-specific processor for DSP applications is not only driven by low-cost requirements, but also needs to fulfil constraints in terms of short development time. MetaCore, a configurable and instruction-level extensible DSP core, can effectively satisfy these requirements by providing a high degree of customization to the given application. In this paper, we present architectural concept of MetaCore and the MetaCore development platform. And we also present the first-generation MetaCore product version, MDSP16, which is a 16-by-16 fixed-point DSP processor. MDSP1.6 was implemented using 0.6 /spl mu/m TLM CMOS technology and has 50 MIPS peak performance.

FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit

This paper describes a VLIW (very long instruction word) geometry processor called FLOVA (FLOating-Point VLIW Architecture) which was developed to accelerate the geometry stage of 3D graphics. FLOVA executes four instructions in one cycle and supports 136 instructions including 35 SIMD (single instruction multiple data) instructions to accelerate the geometry stage. Special features to accelerate transformation and lighting operations in 3D graphics geometry stage are described. FLOVA can calculate the power value of two floating-point numbers in only four clock cycles with a negligible loss of accuracy, compared to over 150 clock cycles in other processors.

Co-development of media-processor and source-level debugger using hardware emulation-based validation

To exploit the development system with a media-processor as soon as possible, the co-development and co-validation of them is very important. We describe the co-development of a media-processor and its source-level debugger, which is necessary to develop multimedia systems. Even through a real chip is available, it takes a long time to validate the functionality of the source-level debugger. Here in this paper, we have adopted hardware emulation for a fast development and validation before a processor is fabricated.

The Effect of Quartz Nano-Particles on the Damage Monitoring of Adhesive Joint at Cryogenic Temperature

Recently, a piezoelectric method using piezoelectric characteristics of epoxy adhesives has been successfully developed for the adhesive joints, which can monitor continuously the damage of adhesively bonded structures without producing any defect induced by inserting a sensor. However, due to low piezoelectric properties of epoxy adhesives, the detection of micro crack was impossible. At the cryogenic temperature, the detection of micro crack is important to estimate the fatigue life because the polymeric adhesives become very brittle. Therefore, in this work, the epoxy adhesive was modified by quartz nano-particles which have much higher piezoelectric properties than the epoxy adhesives. To investigate the effects of quartz nano-particles, the static and dynamic tests of the tubular adhesive joints were performed to compare the joint strength and sensitivity of damage monitoring performance. From the experiment result, it was found that the quartz nano-particles not only improved the joint strength but also increased the sensitivity of damage monitoring performance at cryogenic temperature.

System-on-Chip design using intellectual properties with imprecise design costs

This paper presents an IP-based System-on-Chip (SoC) synthesis framework focusing on how to select intellectual properties (IPs) from different sources and how to integrate the selected IPs using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IPs with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is converted into an equivalent mixed integer linear programming (MILP) model without increasing the computational complexity. Experimental results on an MP3 decoding system show that the IP-centric design space with uncertainty can be successfully explored using the proposed scheme.