Chand R. Viswanathan

Evaluation of plasma damage using fully processed metal–oxide–semiconductor transistors

The device damage during plasma etching is studied in this work using fully processed metal–oxide–semiconductor (MOS) transistors with antennas to accentuate oxide charging effect. The investigation of both charging damage and another damage that occurs during poly gate etching are reported in this article. The susceptibility of plasma damaged n‐MOS and p‐MOS devices to hot carrier stress is shown to be a function of the etch chemistry and etching tool.

Space‐Charge‐Limited Current of Holes in Silicon and Techniques for Distinguishing Double and Single Injection

Space‐charge‐limited (SCL) current of holes has been observed in high‐resistivity silicon at room temperature through proper sample design and suitable choice of an upper limit for electric fields applied in the sample. Joule heating and hot‐carrier effects, which limited the observation of SCL current in previous work, were hardly noticeable in our measurements. Current—voltage characteristics were measured and found to contain an Ohmic portion followed by a region that obeyed the theoretical space‐charge‐limited‐current law J=(9/8)eμpV2/L3. This behavior has been verified for various samples differing in lengths by a factor of 10. The value of the incremental capacitance of the samples, when suitably corrected for fringing capacitance, was found to agree with the value (¾) C predicted by Shao and Wright for SCL currents, where C is the capacitance due to the sample geometry. Values of current were observed to be much greater on some samples than those predicted by the single carrier space‐charge‐limited...

Generation of hole traps in thin silicon oxide layers under high‐field electron injection

The letter reports an observation of a new degradation mechanism in thermal silicon dioxide layers on silicon, namely generation of hole traps under high‐field stressing of metal‐oxide‐semiconductor (MOS) structure. Excess hole trapping due to newly generated hole traps is observed by substrate hot‐hole injection in 9 nm oxide of p‐channel MOS transistors after high‐field Fowler‐Nordheim stress followed by standard post‐metallization annealing in nitrogen. The concentration of generated traps has a weak stress‐polarity dependence and increases with electron fluence during degrading stress. Relaxation behavior under switching oxide fields indicates that the nature of hole trapping sites is different from anomalous positive charge centers.

The characterization of high electron mobility transistors using Shubnikov–de Haas oscillations and geometrical magnetoresistance measurements

Shubnikov–de Haas oscillations and geometrical magnetoresistance measurements are used to determine the two most important parameters, channel concentration and mobility, respectively, for high electron mobility transistors. To deduce useful data from measurements, the theory of the Shubnikov–de Haas oscillation for the two‐dimensional electrons is derived and discussed in detail. The experimental data for the channel concentration as a function of gate voltage is used to check the accuracy of the charge‐control law. We also derive a simple formula of the geometrical magnetoresistance to calculate the mobility for any aspect ratio. The concentration and mobility deduced from the Shubnikov–de Haas and geometrical magnetoresistance measurements give us insight on the nature and properties of the devices. The experimental data shows that the impurity scattering is the dominant mechanism for the low channel concentration. The maximum transconductance occurs at a compromise between the charge‐control ability of the gate voltage and the channel mobility. Near the cutoff region the decrease of the conductivity is due to the decrease of both the channel concentration and the mobility.

Increased hole trapping in gate oxides as latent damage from plasma charging

With aggressive device scaling and the wide use of plasma-assisted processes, the device damage caused by process-induced charging is receiving growing attention, from both basic understanding and technological points of view. The paper presents results of hole-trapping studies in the thin gate oxide of plasma-damaged NMOS and PMOS transistors. In addition to neutral electron traps and passivated interface damage, which are commonly observed in plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. Enhanced hole trapping in the gate oxide of plasma-damaged devices was studied using Fowler - Nordheim stress and substrate hot-hole injection applied to antenna test structures sensitive to process-induced charging. The number of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole-trap generation is based on electrical stress and current flow, forced through the oxide due to charging under plasma etching or ion implantation conditions.

Gate oxide leakage due to temperature accelerated degradation under plasma charging conditions

Plasma-induced gate charging and resulting damage to the gate oxide during fabrication of submicron devices becomes a serious yield and reliability concern, especially when oxide thickness and device dimensions shrink to the nanoscale region. In this paper experimental results from plasma damaged submicron MOS transistors, namely low-level gate leakage and degraded charge-to-breakdown characteristics, are analyzed with respect to conditions of electrical stress. It is demonstrated that wafer temperature is a crucial parameter for charging-induced oxide degradation due to plasma processing. Laboratory experiments simulating plasma charging showed that low-level oxide leakage is the result of oxide breakdown after electrical wear-out under low-level injection conditions. High field stress, performed at 150°C, confirmed that elevated temperature during plasma processing strongly accelerates oxide degradation and even at low-level stress leads to the effects observed in plasma damaged devices.

Leakage Current Due To Plasma Induced Damage In Thin Gate Oxide MOS Transistors

Leakage current was measured on devices with different oxide thickness ranging from 4.5nm to 13nm. Thinner oxide devices exhibited larger leakage, while all devices showed antenna ratio dependence. Detailed measurements were done on 4.5nm oxide devices. We observed high leakage current at low applied voltages in both NMOS and PMOS transistors, caused by charging damage due to plasma processing. Hot carrier measurements were done and the results correlate with leakage current in PMOS transistors having different antenna ratios, while there is no such correlation in NMOS devices. A possible explanation for this difference is given.

Low frequency noise in quantum-well Ge x Si 1-x PMOSFET's

This paper describes the low frequency noise behavior of a quantum-well GexSi1-x p-channel MOSFET. Two noise mechanisms were involved in this buried channel device. At room temperature, generation-recombination (g-r) noise dominates, while at very low temperature, flicker (l/f) noise becomes important.

Direct Measurement of Built‐in Voltage in MOS Structures

It is shown that it is possible to measure directly, using a photoelectric technique, the built‐in voltage in a MOS structure. The experimentally measured values, using this method, are compared with values obtained by another method, and the validity of this method is established.

Oxide thickness dependence of hole trap generation in MOS structures under high-field electron injection

Abstract Hole trapping in the gate oxide of MOS devices causes instabilities of device parameters and serious reliability problems in MOS transistors and memories. In this work, hole traps, generated by high-field electron injection, are studied in thermal oxides in the thickness range below 10 nm. PMOS transistors, after various doses of positive and negative FN injection and post-stress annealing are subjected to substrate hot hole injection to investigate hole trapping kinetics. Parameters of hole traps, generated under the stress, are studied as a function of gate oxide thickness and stress dose.