T. Brozek

Generation of hole traps in thin silicon oxide layers under high‐field electron injection

The letter reports an observation of a new degradation mechanism in thermal silicon dioxide layers on silicon, namely generation of hole traps under high‐field stressing of metal‐oxide‐semiconductor (MOS) structure. Excess hole trapping due to newly generated hole traps is observed by substrate hot‐hole injection in 9 nm oxide of p‐channel MOS transistors after high‐field Fowler‐Nordheim stress followed by standard post‐metallization annealing in nitrogen. The concentration of generated traps has a weak stress‐polarity dependence and increases with electron fluence during degrading stress. Relaxation behavior under switching oxide fields indicates that the nature of hole trapping sites is different from anomalous positive charge centers.

Degraded CMOS hot carrier life time-role of plasma etching induced charging damage and edge damage

There are two different types of damage resulting from plasma etching (oxide charging damage and plasma edge damage) which can degrade the reliability of CMOS devices. The oxide charging damage is due to plasma induced Fowler-Nordheim current flowing through gate oxide, while edge damage is due to direct plasma exposure during the poly-Si overetch period. This paper addresses the influence of plasma etching-induced damage on device susceptibility to hot-carrier (HC) degradation. The role of oxide charging damage and that of edge damage are isolated and characterized for both n-channel and p-channel MOS devices, and the corresponding dependence of HC lifetime is analyzed. Finally, the effect of plasma damage on HC degradation of ring oscillators is studied.

Hole trap generation in the gate oxide due to plasma-induced charging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%.

Temperature accelerated gate oxide degradation under plasma-induced charging

Gate oxide charging during plasma processing of submicron devices becomes a serious yield and reliability concern, especially when oxide thickness and device dimensions shrink to the nanoscale region. This paper shows that wafer temperature is a crucial parameter for charging-induced oxide degradation due to plasma processing. Experimental results from plasma damaged submicron MOS transistors, namely low-level gate leakage and degraded charge-to-breakdown characteristics are analyzed from the point of view of conditions of electrical stress. Laboratory experiments simulating plasma charging, performed at 150/spl deg/C, confirmed that elevated temperature during plasma processing strongly accelerates oxide degradation and even at low-level stress leads to effects observed in plasma damaged devices.

Role of temperature in process-induced charging damage in sub-micron CMOS transistors

High-field stressing of the gate oxide in sub-micron MOS transistors at various stress temperatures was used to simulate process-induced charging and latent damage creation during some of the processing steps. By studying degradation of transistor parameters in damaged devices it has been shown that the temperature of the wafer, at which devices experience charging effects, significantly enhances the amount of latent damage remaining in the Si-SiO/sub 2/ system after full processing. The increased density of neutral electron traps in the oxide and enhanced susceptibility of the interface to degradation in transistors, deteriorated at elevated temperatures, correlate with charge-to-breakdown reduction in both NMOS and PMOS transistors.

Gate oxide leakage due to temperature accelerated degradation under plasma charging conditions

Plasma-induced gate charging and resulting damage to the gate oxide during fabrication of submicron devices becomes a serious yield and reliability concern, especially when oxide thickness and device dimensions shrink to the nanoscale region. In this paper experimental results from plasma damaged submicron MOS transistors, namely low-level gate leakage and degraded charge-to-breakdown characteristics, are analyzed with respect to conditions of electrical stress. It is demonstrated that wafer temperature is a crucial parameter for charging-induced oxide degradation due to plasma processing. Laboratory experiments simulating plasma charging showed that low-level oxide leakage is the result of oxide breakdown after electrical wear-out under low-level injection conditions. High field stress, performed at 150°C, confirmed that elevated temperature during plasma processing strongly accelerates oxide degradation and even at low-level stress leads to the effects observed in plasma damaged devices.

Leakage Current Due To Plasma Induced Damage In Thin Gate Oxide MOS Transistors

Leakage current was measured on devices with different oxide thickness ranging from 4.5nm to 13nm. Thinner oxide devices exhibited larger leakage, while all devices showed antenna ratio dependence. Detailed measurements were done on 4.5nm oxide devices. We observed high leakage current at low applied voltages in both NMOS and PMOS transistors, caused by charging damage due to plasma processing. Hot carrier measurements were done and the results correlate with leakage current in PMOS transistors having different antenna ratios, while there is no such correlation in NMOS devices. A possible explanation for this difference is given.

LDD charge pumping-direct measurement of interface states in the overlap region

In submicron MOS devices, the degradation of the region where the gate overlaps the LDD (lightly doped drain) region determines hot carrier reliability as well as off-state leakage current. A quantitative experimental technique (LDD charge pumping) to characterize the interface states in the overlap region is demonstrated in this work. The usefulness of this technique is then demonstrated by application to the study of hot carrier and Fowler-Nordheim stresses as well as plasma exposure.

Charge injection using gate-induced-drain-leakage current for characterization of plasma edge damage in CMOS devices

In this paper, we describe the application of gate-induced-drain-leakage (GIDL) current for the characterization of gate edge damage which occurs during the plasma etch processes. We show from experimental and simulation results that when the channel is biased in accumulation and with the drain-substrate junction reverse biased, charge injection is localized in the gate-drain overlap region. Under this localized charge injection (LCI) mode of operation, the gate voltage is a function of edge oxide thickness which in turn can be related to the plasma damage received during the poly-etch and subsequent spacer oxide formation. The detailed mechanism of localized charge injection for a study of plasma edge damage is explained along with the experimental demonstration of this technique using submicron MOSFETs.

Localized charge injection through the gate oxide over gate-drain overlap region: mechanism, device dependence, and application for device diagnostics

The paper presents a study of localized charge injection through the gate oxide in MOS transistors with 4.5-13 nm thick oxides and its application for device diagnostics. The injection, localized over a gate/drain overlap, is investigated in a high-field GIDL (Gate-Induced Drain Leakage) regime in both NMOS and PMOS devices and is found to be a suitable diagnostic tool for monitoring one of the many process-dependent parameters-the thickness of the gate oxide at the gate edge. Correlation between edge oxide thickening, plasma edge damage, and the performance and reliability of CMOS devices is presented.