Chandan Yadav

Robust Surface-Potential-Based Compact Model for GaN HEMT IC Design

We present an accurate and robust surface-potential-based compact model for simulation of circuits designed with GaN-based high-electron mobility transistors (GaN HEMTs). An accurate analytical surface-potential calculation, which we developed, is used to develop the drain and gate current model. The model is in excellent agreement with experimental data for both drain and gate current in all regions of device operation. We show the correct physical behavior and mathematical robustness of the model by performing various benchmark tests, such as DC and AC symmetry tests, reciprocity test, and harmonic balance simulations test. To the best of our knowledge, this is the first time a GaN HEMT compact model passing a range of benchmark tests has been presented.

Recent enhancements in BSIM6 bulk MOSFET model

In this paper, we discuss the recent enhancements made in the BSIM6 bulk MOSFET model. BSIM6 is the latest compact model of bulk MOSFET from BSIM group which have body referenced charge based core. Junction capacitance model is improved over BSIM4 and is infinitely continuous around Vbs=Vbd=0V. Symmetry of the model is successfully validated by performing Gummel Symmetry Test (GST) in DC and symmetry test for capacitances in AC. Self heating model is also included in BSIM6 and test results are reported. Model capabilities are compared against an advanced 40nm CMOS technology and it is observed that simulated results are in excellent agreement with the measured data.

Modeling of GaN-Based Normally-Off FinFET

In this letter, a macromodel for normally-off (enhancement mode) AlGaN/GaN-based FinFET (2-DEG channel at top with two MOS like sidewall channels) is proposed. AlGaN/GaN-based FinFET devices have improved gate control on the channel due to additional sidewall gates compared with planar structures, but device characteristics exhibit strong nonlinear dependence on fin-width. The proposed model captures both 2-DEG and sidewall channel conduction as well as the fin-width dependency on device characteristics. Model shows excellent agreement with state-of-the-art experimental data.

Capacitance Modeling in III–V FinFETs

We present a physics-based model of charge density and capacitance for III-V channel double-gate nMOSFETs. The developed model accurately accounts for the impact of quantum capacitance on gate capacitance with applied gate voltage including the steplike behavior with sub-band population. The presented model is in excellent agreement with the self-consistent Schrödinger-Poisson simulation data of InGaAs channel double-gate MOSFET.

Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model

In this paper, an analytical model of threshold voltage for bulk MOSFET is developed. The model is derived from the physical charge-based core of BSIM6 MOSFET model, taking into account short channel effects, and is intended to be used in commercial SPICE simulators for operating point information. The model is validated with measurement data from IBM 90-nm technology node using various popular threshold voltage extraction techniques, and good agreement is obtained.

Compact Modeling of Transition Metal Dichalcogenide based Thin body Transistors and Circuit Validation

In this paper, we present a compact model for surface potential and drain current in transition metal dichalcogenide (TMD) channel material-based n-type and p-type FETs. The model considers 2-D density of states and Fermi–Dirac statistics along with drift-diffusion transport model and includes velocity saturation and trap state effects. The developed model has been implemented in Verilog-A and is applicable for symmetric double gate as well as top-gated TMD-on-insulator FETs. The presented model is extensively validated with simulation as well as experimental data for different TMD materials-based FETs and shows excellent agreement with both the simulation and the experimental data. We further validate the model at circuit level using experimental data of MoS2 FET-based inverter.

Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor

Quantum capacitance is expected to have strong impact on the gate capacitance in III-V devices. In this paper, we present a comprehensive analysis of the quantum capacitance for III-V ultra-thin body with thin box transistor. The results show the presence of quantum capacitance effect and step like behavior due to individual contribution of sub-bands in the gate capacitance. We discuss the impact of various parameters such as insulator thickness, channel (body) thickness on the capacitance with positive and negative back gate biases.

Modeling of Charge and Quantum Capacitance in Low Effective Mass III-V FinFETs

In this paper, we present a compact model for semiconductor charge and quantum capacitance in III-V channel FETs. With III-V being viewed as the most promising candidate for future technology node, a compact model is needed for their circuit simulation. The model presented in this paper addresses this need and is completely explicit and computationally efficient which makes it highly suitable for SPICE implementation. The proposed model is verified against the numerical solution of coupled Schrödinger-Poisson equation for FinFET with various channel thickness and effective mass.

BSIM-IMG with improved surface potential calculation recipe

In this paper, we have reported the improved surface potential calculation in the BSIM-IMG model for FDSOI MOSFETs. Model validation is done with the experimental data provided by Low-power Electronics Association and Project (LEAP). The model shows accurate behavior for C-V and I-V characteristics while keeping smooth behavior for their higher order derivatives. Model has smooth transition from weak inversion to strong inversion and satisfies DC and AC symmetry tests.

Compact Modeling of Charge, Capacitance, and Drain Current in III–V Channel Double Gate FETs

In this paper, we present a surface potential based compact modeling of terminal charge, terminal capacitance, and drain current for III–V channel double gate field-effect transistor (DGFET) including the effect of conduction band nonparabolicity. The proposed model is developed accounting for the two-dimensional density of states and includes the effect of quantum capacitance associated with the low density of states channel material. In addition, model incorporates contribution of the first two sub-bands and efficiently captures the step like behavior appearing in the gate capacitance and transconductance with population of the higher sub-bands. The behavior of bias-dependent terminal capacitances and drain current is verified with the numerical simulation data of InGaAs channel DGFET and shows a close agreement with the simulation data.