Chandler Todd McDowell

A Test Structure for Characterizing Local Device Mismatches

We present a test structure for statistical characterization of local device mismatches. The structure contains densely populated SRAM devices arranged in an addressable manner. Measurements on a test chip fabricated in an advanced 65 nm process show little spatial correlation. We vary the nominal threshold voltage of the devices by changing the threshold-adjust implantations and observe that the ratio of standard deviation to mean gets worse with threshold scaling. The large variations observed in the extracted threshold voltage statistics indicate that the random doping fluctuation is the likely reason behind mismatch in the adjacent devices

Test structures for delay variability

With continued technology scaling, yield loss due to timing variation is becoming a significant concern. In particular, random and systematic process variation in devices and interconnect results in variable delay and operating speed along different logic and signal paths; these variations can erode timing windows and ultimately contribute to circuit failure. In this work, a test structure methodology is developed to support the evaluation of process variation and its impact on circuit speed.A newly designed variation test chip enables relatively simple measurement and evaluation of timing variation resulting from process and layout-induced variation. First, the fundamental test structure is a nine-stage ring oscillator (RO); a frequency-divided readout of the RO frequency serves as a clearly defined measure of circuit speed. A large family of ring oscillator test structures has been designed, where each structure is made sensitive to a particular device or interconnect variation source. Front-end-of-line (FEOL) or device variation sensitive structures enable examination of channel length variation as a function of different layout practices, including gate length (finger width), spacing between multiple fingers, orientation (vertical or horizontal), and density of poly fill. Back-end-of-line (BEOL) or interconnect sensitive structures enable examination of variation in dielectric or metal thickness at different metal levels and impact on interconnect capacitance.The second key element of the test structure methodology is a scan-chain architecture enabling independent operation and readout of replicated ring oscillator test structures. In this second version test chip, designed and fabricated in

Enhanced thermoelectric cooling at cold junction interfaces

0.25 m technology, over 2000 ring oscillators per chip can be measured using simple digital control and readout circuitry interfaced to the packaged chip. The scan chain approach involves reading in a control word to each ring oscillator, which specifies if that oscillator is to operate and if the RO frequency is to be put onto an output bus into frequency division and output circuitry. Additional test chip design elements include separate ring oscillator and control logic power grids, so that the frequency dependence of the ring oscillators on power supply voltage can also be measured, enabling separation of channel length and threshold voltage variation contributions.A

A double precision floating point multiply

0.25 µm version of the test chip has been fabricated, and measurement and statistical analysis of 35 chips have been successfully conducted. Results indicate that within-wafer variation continues to be larger than within-chip variation; however, systematic spatial patterns and layout-dependent variations within the chip are substantial and of particular concern in timing (which depends on matched signal delays across a chip or logic block). The test chip can be ported to other advanced technologies to provide information on layout-dependent and spatially-dependent process variation sources of timing variation, to aid in statistical timing analysis as well as help specify layout practices and design rules to minimize variation.

Limited switch dynamic logic circuits for high-speed low-power circuit design

We describe a thermoelectric device structure that confines the thermal gradients and electric fields at the boundaries of the cold end, and exploits the reduction of thermal conductivity at the interfaces and the poor electron-phonon coupling at the junctions. The measured temperature–current and voltage–current characteristics of a prototype cold point-contact thermoelectric cooler based on a p-type Bi0.5Sb1.5Te3 and n-type Bi2Te2.9Se0.1 material system indicate an enhanced thermoelectric figure-of-merit ZT in the range of 1.4–1.7 at room temperature.

An 8GHz floating-point multiply

A 2.2GHz 53/spl times/54 bit pipelined multiplier is fabricated in 130nm CMOS technology with an area of 0.15mm/sup 2/. The circuit implementation results in a 50% size reduction over the previously reported values. The circuit operates at 2.2GHz and uses 522mW at 80% switching factor, 1.2V supply and 25/spl deg/C.

Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs

This paper describes a new circuit family--limited switch dynamic logic (LSDL). LSDL is a hybrid between a dynamic circuit and a static latch that combines the desirable properties of both circuit families. The paper also describes many enhancements and extensions to LSDL that increase its logical capability. Finally, it presents the results of two multiplier designs, one fabricated in 130- nm technology and one in 90-nm technology. The 130- and 90-nm designs respectively reach speeds up to 2.2 GHz and 8 GHz.

A low latency and low power dynamic Carry Save Adder

The implementation of the mantissa portion of a floating-point multiply (54/spl times/54b) is described. The 0.124mm/sup 2/ multiplier is implemented using limited switch dynamic logic and operates at speeds up to 8GHz in a 90nm SOI technology. The multiplier dissipates between 150mW and 1.8W as it scales between 2GHz and 8GHz.

The case for power management in web servers

We present a critical study of the impact of gate tunneling currents on the yield of a 65nm PD/SOI SRAM cell. Gate-leakage tunneling currents are obtained from hardware measurements. It is shown that the gate-leakage impact on the cell yield can be non-monotonic, and is appreciable even for non-defective devices. It is also shown that further design optimizations such as the operating voltage or bitline loading can help alleviate the gate-leakage impact on yield. Mixture importance sampling is used to estimate yield, and threshold voltage variations to model random fluctuation effects are extrapolated from hardware

Method and apparatus for reducing power consumption for power supplied by a voltage adapter

This paper presents a 4-to-2 Carry Save Adder (CSA) using dynamic logic and the Limited Switch Dynamic Logic (LSDL) circuit family. Adders are a crucial portion of all floating-point units, since they form the base element of all arithmetic functions. The 4-to-2 circuits reported previously do not meet the requirements of the next generation of processors. The adder presented here is built using a dynamic circuit style that improves performance significantly. Further a latching element after each dynamic evaluation node controls the power of the dynamic circuits. In this paper we project some of the salient features of the LSDL circuit family by comparing this 4-2 circuit with the most similar static implementation. Use of the LSDL circuit family displays significant improvement not only in terms of performance but also with respect to power dissipation, leakage and area.